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參數(shù)資料
| 型號： | S24163SBT |
| 廠商： | Summit Microelectronics, Inc. |
| 英文描述： | Precision RESET Controller with 16K I2C Memory |
| 中文描述： | 精密復位控制器的I2C與16K的記憶 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大小： | 169K |
| 代理商： | S24163SBT |
S24163
5
2014 2.1 8/2/00
FIGURE 6. PAGE/BYTE WRITE MODE
WRITE OPERATIONS
The S24163 allows two types of write operations: byte
write and page write. The byte write operation writes a
single byte during the nonvolatile write period (t
WR
). The
page write operation allows up to 16 bytes in the same
page to be written during t
WR
.
Byte WRITE
After the slave address is sent (to identify the slave
device, specify high order word address and a read or
write operation), a second byte is transmitted which
contains the low 8 bit addresses of any one of the 2,048
words in the array.
Upon receipt of the word address, the S24163 responds
with an ACKnowledge. After receiving the next byte of
data, it again responds with an ACKnowledge. The master
then terminates the transfer by generating a STOP condi-
tion, at which time the S24163 begins the internal write
cycle.
While the internal write cycle is in progress, the S24163
inputs are disabled, and the device will not respond to any
requests from the master. Refer to Figure 6 for the
address, ACKnowledge and data transfer sequence.
Page WRITE
The S24163 is capable of a 16-byte page write operation.
It is initiated in the same manner as the byte-write
operation, but instead of terminating the write cycle after
the first data word, the master can transmit up to 15 more
words of data. After the receipt of each word, the S24163
will respond with an ACKnowledge.
The S24163 automatically increments the address for
subsequent data words. After the receipt of each word, the
four low order address bits are internally incremented by
one. The high order five bits of the address byte remain
constant. Should the master transmit more than sixteen
words, prior to generating the STOP condition, the ad-
dress counter will
“
roll over,
”
and the previously written
data will be overwritten. As with the byte-write operation,
all inputs are disabled during the internal write cycle.
Refer to Figure 6 for the address, ACKnowledge and data
transfer sequence.
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
5
D
6
D
4
D
0
D
3
D
2
D
1
S
T
A
R
T
Word Address
Data Byte n
Data Byte n+15
S
T
O
P
A
C
K
Acknowledges Transmitted from
24163 to Master Receiver
Slave Address
Device
Type
Address
Read/Write
0= Write
A10,A9,A8
SDA
Bus
Activity
A
C
K
A
C
K
Master Sends Read
Request to Slave
Master Writes Word
Address to Slave
1 0 1 0
0
Data Byte n+1
A
C
K
Master Writes
Data to Slave
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Master Transmitter
to
Slave Receiver
Master Transmitter
to
Slave Receiver
Shading Denotes
24163
SDA Output Active
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
Slave Transmitter
to
Master Receiver
Master Transmitter
to
Slave Receiver
Slave Transmitter
to
Master Receiver
Master Writes
Data to Slave
Master Writes
Data to Slave
Acknowledges Transmitted from
24163 to Master Receiver
If single byte-write only,
Stop bit issued here.
A
10
A
9
R
W
A
C
K
A
8
2014 T fig06 2.0
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