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參數(shù)資料
| 型號： | S2076 |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | Quad Fibre Channel Transceiver(四光纖通道收發(fā)器) |
| 中文描述： | 四光纖通道收發(fā)器（四光纖通道收發(fā)器） |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 300K |
| 代理商： | S2076 |
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6
S2076
QUAD FIBRE CHANNEL TRANSCEIVER
October 13, 2000 / Revision B
Figure 5 demonstrates the flexibility afforded by the
S2076. A low jitter reference is provided directly to
the S2076 at either 1/10 or 1/20 the serial data rate.
This insures minimum jitter in the synthesized clock
used for serial data transmission. A system clock
output at the parallel word rate, TCLKO, is derived
from the PLL and provided to the upstream circuit as
a system clock. This clock can be buffered as re-
quired without concern about added delay. There is
no phase requirement placed upon TCLKO and the
TBCx clock, which is provided back to the S2076,
other than they remain within
±
3ns of the phase rela-
tionship established at reset.
The S2076 also supports the traditional REFCLK
clocking found in Fibre Channel applications and is
illustrated in Figure 6.
Half Rate Operation
The S2076 supports full and 1/2 rate operation for all
modes of operation. When RATE is LOW, the S2076
serial data rate equals the VCO frequency. When
RATE is HIGH, the VCO is divided by 2 before being
provided to the chip. Thus the S2076 can support
Fibre Channel and serial backplane functions at both
full and 1/2 the VCO rate.
Parallel-to-Serial Conversion
The 10-bit parallel data handled by the S2076 device
should be from a DC-balanced encoding scheme,
such as the 8B/10B transmission code, in which in-
formation to be transmitted is encoded, 8 bits at a
time, into a 10-bit transmission character and must
be compliant with ANSI X3.230 FC-PH (Fibre Chan-
nel Physical and Signaling Interface).
The 8B/10B transmission code includes serial en-
coding and decoding rules, special characters, and
error control. Information is encoded, 8 bits at a time,
into a 10 bit transmission character. The characters
defined by this code ensure that short run lengths
and enough transitions are present in the serial bit
stream to make clock recovery possible at the re-
ceiver. The encoding also greatly increases the like-
lihood of detecting any single or multiple errors that
might occur during the transmission and reception of
data
1
.
Table 3 identifies the mapping of the 8B/10B charac-
ters to the data inputs of the S2076. The S2076 will
serialize the parallel data for each channel and will
transmit bit “a” or DIN[0] first.
Frequency Synthesizer (PLL)
The S2076 synthesizes a serial transmit clock from
the reference signal provided. The S2076 will obtain
phase and frequency lock within 2500 bit times after
the start of receiving reference clock inputs. Reliable
locking of the transmit PLL is assured, but a lock-
detect output is NOT provided.
e
B
a
D
r
]
N
]
U
O
I
D
D
0
1
2
3
4
5
6
7
8
9
.
e
.
p
B
0
1
B
8
a
b
c
d
e
i
f
g
h
j
REFCLK
S2076
TBCx
DINx[0:9]
REF
OSCILLATOR
MAC
ASIC
TCLKO
PLL
106.25 MHz
Figure 6. FC DIN Clocking with REFCLK
Table 3. Data to 8B/10B Alphabetic Representation
1. A.X. Widner and P.A. Franaszek, "A Byte-Oriented DC Bal-
anced (0,4) 8B/10B Transmission Code," IBM Research Report
RC9391, May 1982.
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