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參數資料
| 型號： | S2060 |
| 廠商： | MICROSEMI CORP-LAWRENCE |
| 元件分類： | 參考電壓二極管 |
| 英文描述： | Silicon Power Rectifier |
| 中文描述： | 16 A, 600 V, SILICON, RECTIFIER DIODE, DO-203AA |
| 封裝： | DO-4, 1 PIN |
| 文件頁數： | 1/22頁 |
| 文件大?。?/td> | 693K |
| 代理商： | S2060 |
1
S2060
S2060
GIGABIT ETHERNET TRANSCEIVER
March 7, 2001 / Revision H
DEVICE
SPECIFICATION
FEATURES
Operating rate
1250 MHz (Gigabit Ethernet) line rates
Half and full VCO output rates
Functionally compliant IEEE 802.3z Gigabit
Ethernet standard
Transmitter incorporating Phase-Locked Loop
(PLL) clock synthesis from low speed reference
Receiver PLL provides clock and data recovery
10-bit parallel TTL compatible interface
Low-jitter serial LVPECL compatible interface
Local loopback
Single +3.3 V supply, 620 mW power dissipation
64 PQFP or TQFP package
Continuous downstream clocking from receiver
Drives 30 m of Twinax cable directly
APPLICATIONS
Workstation
Frame buffer
Switched networks
Data broadcast environments
Proprietary extended backplanes
GENERAL DESCRIPTION
The S2060 transmitter and receiver chip facilitates
high speed serial transmission of data over fiber op-
tic, coax, or twinax interfaces. The device conforms
to the requirements of the IEEE 802.3z Gigabit
Ethernet specification, and runs at 1250.0 Mbps data
rates with an associated 10-bit data word.
The chip provides parallel-to-serial and serial-to-par-
allel conversion, clock generation/recovery, and
framing for block encoded data. The on-chip transmit
PLL synthesizes the high-speed clock from a low-
speed reference. The on-chip receive PLL performs
clock recovery and data re-timing on the serial bit
stream. The transmitter and receiver each support
differential LVPECL compatible I/O for copper or fi-
ber optic component interfaces with excellent signal
integrity. Local loopback mode allows for system di-
agnostics. The chip requires a +3.3 V power supply
and dissipates typically 620 mW.
The S2060 can be used for a variety of applications
including Gigabit Ethernet, serial backplanes, and
proprietary point-to-point links. Figure 1 shows a
typical configuration incorporating the chip.
Figure 1. System Block Diagram
S2060
Gigabit
Ethernet
Controller
Optical
Tx
Optical
Rx
Optical
Tx
Optical
Rx
S2060
Gigabit
Ethernet
Controller
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PDF描述 |
|---|---|
| S2061 | Serial Backplane Transceiver(用于高速串行數據傳送的收發(fā)器) |
| S2062 | Dual Serial Backplane Transceiver(用于以太網，光纖通道高速串行數據傳送的雙收發(fā)器) |
| S2064 | Quad Serial Backplane Device(用于以太網，光纖通道高速串行數據傳送的四收發(fā)器) |
| S2065 | Quad Serial Backplane Device with Dual I/O(帶雙傳送接收串行I/O的四收發(fā)器) |
| S2066 | Quad GigaBit Ethernet Transceiver(四千兆位以太網收發(fā)器) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| S2060A | 制造商:AppliedMicro 功能描述:GIGABIT ETHERNET/FIBRE CHANNEL TRANSCEIVER |
| S2060A (RECTIFIER) | 制造商:RCA 功能描述:Silicon Controlled Rectifier, 100 Volt, 2.75A, TO-220 |
| S2060A (TRANSCEIVER) | 制造商:AppliedMicro 功能描述:DATACOM, ETHERNET TRANSCEIVER, 64 Pin Plastic QFP |
| S2060AH | 制造商:RCA 功能描述:2060AH |
| S2060B | 制造商:AppliedMicro 功能描述:GIGABIT ETHERNET/FIBRE CHANNEL TRANSCEIVER |
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