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參數(shù)資料
| 型號(hào)： | S2054 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | Fibre Channel and GigaBit Ethernet Transceiver(帶雙接收和發(fā)送串行I/O的光纖通道和千兆位以太網(wǎng)收發(fā)器) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封裝： | 10 X 10 MM, PLASTIC, QFP-64 |
| 文件頁(yè)數(shù)： | 3/15頁(yè) |
| 文件大?。?/td> | 306K |
| 代理商： | S2054 |
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FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
S2054
March 21, 2001 / Revision A
3
REFCLKP/N
TREFCLK
(Input)
RBC0
(Output)
COM_DET
(Output)
PARALLEL
DATA BUS
(Input)
PARALLEL
DATA BUS
(Output)
SERIAL DATA
K28.5
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
K28.5
K28.5
K28.5
K28.5
K28.5
RBC1
(Output)
INPUT TIMING
OUTPUT TIMING
Figure 4. Functional Waveform (1250 and 1062.5 Mbit/sec)
TRANSMITTER FUNCTIONAL
DESCRIPTION
The S2054 transmitter accepts parallel input data and
serializes it for transmission over fiber optic or coaxial
cable media. The chip is fully compatible with the ANSI
X3T11 Fibre Channel standard, and supports the Fi-
bre Channel and Gigabit Ethernet data rates of 1250
and 1062 Mbit/sec. (See Figure 3.)
Data Input
Transmit data is provided to the S2054 as 10-bit wide
LVTTL. Data is clocked into the S2054 on the rising
edge of REFCLK.
Parallel/Serial Conversion
The parallel-to-serial converter takes in 10-bit wide
data from the input latch and converts it to a serial
data stream. Parallel data is latched into the transmitter
using the reference clock. The data is then clocked
synchronous to the clock synthesis unit serial clock
into the serial output shift register. The shift register
is clocked by the internally generated bit clock which
is 10x the reference clock input frequency. D0 is trans-
mitted first as described in annex N and Tables 22
and 23 of FC-PH. Table 1 shows the mapping of the
parallel data to the 8B/10B codes. Two serial data
outputs are provided.
Reference Clock Input
The reference clock input must be supplied with ei-
ther a differential LVPECL (REFCLKP/N) or
single-ended LVTTL (TREFCLK) clock source with
100 PPM tolerance to assure that the transmitted data
meets the Fibre Channel frequency limits. The inter-
nal serial clock is frequency locked to the reference
clock (125.00 or 106.25 MHz).
Data Byte
9
8
7
6
5
4
3
2
1
0
TX[0:9] or
RX[0:9]
8b/10b alphabetic
representation
j
h
g
f
i
e
d
c
b
a
Table 1. Data Mapping to 8b/10b Alphabetic Representation
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S2055A | SILICON DIFFUSED POWER TRANSISTOR |
| S2057 | Port Bypass Circuit for Fibre Channel and GigaBit Ethernet(用于光纖通道和千兆位以太網(wǎng)的端口旁路電路) |
| S2058 | Port Bypass and Repeater for Fibre Channel Arbitrated Loop(用于光纖通道仲裁環(huán)路的端口旁路電路和中繼器) |
| S2060 | GIGABIT ETHERNET TRANSCEIVER |
| S2060A | GIGABIT ETHERNET TRANSCEIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S2054AG4 | 制造商:TYAN 功能描述:M-ATX SOCKET-370 INTEL 810 - Bulk |
| S2055 | 制造商:ISC 制造商全稱:Inchange Semiconductor Company Limited 功能描述:Silicon NPN Power Transistors |
| S2055A | 制造商:SAVANTIC 制造商全稱:Savantic, Inc. 功能描述:Silicon NPN Power Transistors |
| S2055AF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SILICON DIFFUSED POWER TRANSISTOR |
| S2055F | 制造商:ISC 制造商全稱:Inchange Semiconductor Company Limited 功能描述:Silicon NPN Power Transistors |
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