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參數資料
| 型號： | S2054 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 網絡接口 |
| 英文描述： | Fibre Channel and GigaBit Ethernet Transceiver(帶雙接收和發(fā)送串行I/O的光纖通道和千兆位以太網收發(fā)器) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封裝： | 10 X 10 MM, PLASTIC, QFP-64 |
| 文件頁數： | 2/15頁 |
| 文件大?。?/td> | 306K |
| 代理商： | S2054 |
2
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
S2054
March 21, 2001 / Revision A
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figure 4. A block diagram showing the basic chip
operation is shown in Figure 3.
Loopback
Local loopback is supported by the chip, and pro-
vides a capability for performing offline testing of the
interface to ensure the integrity of the serial channel
before enabling the transmission medium. It also al-
lows for system diagnostics.
S2054 OVERVIEW
The S2054 transmitter and receiver provide serializa-
tion and deserialization functions for block-encoded
data to implement a Fibre Channel interface. Opera-
tion of the S2054 is straightforward, as depicted in
Figure 2. The sequence of operations is as follows:
Transmitter
1. 10-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver
1. Clock and data recovery from serial input
2. Serial-to-parallel conversion
3. Frame detection
4. 10-bit parallel output
The 10-bit parallel data handled by the S2054 device
should be from a DC-balanced encoding scheme, such
as the 8B/10B transmission code, in which informa-
tion to be transmitted is encoded 8 bits at a time into
10-bit transmission characters
1
, and be compliant with
ANSI X3.230 FC-PH (Fibre Channel Physical and Sig-
naling Interface).
1. A.X. Widmer and P.A. Franaszek, “A Byte-Oriented DC Balanced (0,4) 8B/10B Transmission Code,” IBM Research Report RC 9391,
May 1982.
Figure 2. Interface Diagram
Parallel
Data In
S2054
Transceiver
REFCLK
Serial
Data In
RCVSEL
RBC0/1
Parallel
Data Out
COM_DET
Serial
Data Out
0
1
0
1
TESTEN
TX [0:9]
10
10
PLL CLOCK
MULTIPLIER
F0 = F1 X 10
SHIFT
REGISTER
TX0P/N
EWRAP
TX1P/N
D
Q
PLL CLOCK
RECOVERY
3:1
D
10
2
2
2
2
D
BITCLK
Q
COM_DET
DETECT
LOGIC
CONTROL
LOGIC
RX0P/N
REFCLKP/N
TREFCLK
RX1P/N
TP/N
EWRAP
-LCK_REF
RCVSEL
EN_CDET
RX[0:9]
RBC1
COM_DET
RBC0
SHIFT
REGISTER
Input
Latch
Figure 3. Functional Block Diagram
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| S2055A | SILICON DIFFUSED POWER TRANSISTOR |
| S2057 | Port Bypass Circuit for Fibre Channel and GigaBit Ethernet(用于光纖通道和千兆位以太網的端口旁路電路) |
| S2058 | Port Bypass and Repeater for Fibre Channel Arbitrated Loop(用于光纖通道仲裁環(huán)路的端口旁路電路和中繼器) |
| S2060 | GIGABIT ETHERNET TRANSCEIVER |
| S2060A | GIGABIT ETHERNET TRANSCEIVER |
相關代理商/技術參數 |
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| S2054AG4 | 制造商:TYAN 功能描述:M-ATX SOCKET-370 INTEL 810 - Bulk |
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| S2055A | 制造商:SAVANTIC 制造商全稱:Savantic, Inc. 功能描述:Silicon NPN Power Transistors |
| S2055AF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SILICON DIFFUSED POWER TRANSISTOR |
| S2055F | 制造商:ISC 制造商全稱:Inchange Semiconductor Company Limited 功能描述:Silicon NPN Power Transistors |
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