參數(shù)資料
型號(hào): S2057
廠商: APPLIEDMICRO INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Port Bypass Circuit for Fibre Channel and GigaBit Ethernet(用于光纖通道和千兆位以太網(wǎng)的端口旁路電路)
中文描述: SPECIALTY TELECOM CIRCUIT, PDSO20
封裝: 4.40 X 6.50 MM, 0.90 MM HEIGHT, TSSOP-20
文件頁(yè)數(shù): 1/9頁(yè)
文件大?。?/td> 98K
代理商: S2057
1
S2057
S2057
PORT BYPASS CIRCUIT FOR FIBRE CHANNEL AND GIGABIT ETHERNET
PORT BYPASS CIRCUIT FOR FIBRE CHANNEL AND GIGABIT ETHERNET
August 8, 2000 / Revision C
FEATURES
Supports ANSI X3T11 1.0625 Gbps FCALdisk
attach
ANSI x3T11 Fibre Channel Compatible
IEEE 802.3z Gigabit Ethernet Compatible
1250 Mbps (Gigabit Ethernet) operation
Fully differential for minimum deterministic
jitter accumulation (10 ps nominal)
TTL Bypass Select
High speed LVPECL I/O
0.2 W Typical power dissipation
3.3 V power supply
20-pin TSSOP
GENERAL DESCRIPTION
The S2057 is a single channel Port Bypass Circuit
(PBC), designed to minimize jitter accumulation by
providing a high bandwidth fully differential data path.
Primary application is in Fibre Channel Arbitrated Loop
(FC-AL) disk arrays to allow hot swapping of FC-AL
drives. The S2057 is designed to support 1.0625 Gbps
and 1.25 Gbps data rates.
The S2057 is a high speed 2:1 multiplexer with 2 modes
of operation: Normal and Bypass. A block diagram is
shown in Figure 1, and a system diagram showing the
S2057 in a single loop of a disk array is shown in Figure 2.
A disk drive connects on the Disk Drive input and output
ports (DDIP/N, DDOP/N), while the INP/N and OUTP/
N ports connect to the upstream and downstream
OUT P/N
SEL
DDI P/N
DDO P/N
IN P/N
1
0
PBC
Figure 1. S2057 Block Diagram
1
L
E
S
T
U
O
O
D
D
0
N
I
N
I
1
I
D
D
N
I
Table 1. Truth Table
DEVICE
SPECIFICATION
devices in the loop. Normal mode is enabled by setting
the SEL pin ACTIVE, which includes the disk in the loop
via the DDI/DDO ports. When the disk drive is either
absent or non-functional, Bypass mode is selected by
setting the SEL pin INACTIVE. This routes data directly
from IN to OUT, bypassing the disk ports. Direct attach
Fibre Channel Disk Drives have an “LRC Interlock”
signal designed to directly control the select function.
Table 1 is a truth table describing the data flow through
the S2057.
Jitter Performance
The primary AC parameter of importance is determinis-
tic jitter accumulation (data eye degradation) inserted
by the port bypass circuit. The S2057 utilizes high
bandwidth, low skew differential circuitry to provide
symmetric rise and fall times and excellent noise immu-
nity. This results in a nominal deterministic jitter accu-
mulation of
±
10 ps.
For arrays of disk drives greater than 4, it is recom-
mended that the S2057 be cascaded with the S2058
(Port Bypass with repeater) in a ratio of 4:1 to perform
clock and data retiming. This insures optimal jitter
performance for the disk array system.
相關(guān)PDF資料
PDF描述
S2058 Port Bypass and Repeater for Fibre Channel Arbitrated Loop(用于光纖通道仲裁環(huán)路的端口旁路電路和中繼器)
S2060 GIGABIT ETHERNET TRANSCEIVER
S2060A GIGABIT ETHERNET TRANSCEIVER
S2060B GIGABIT ETHERNET TRANSCEIVER
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