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參數(shù)資料
| 型號(hào)： | S2052 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 網(wǎng)絡(luò)接口 |
| 英文描述： | Fibre Channel and GigaBit Ethernet Transceiver(用于高速串行數(shù)據(jù)傳送的光纖通道和千兆位以太網(wǎng)收發(fā)器) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁(yè)數(shù)： | 2/15頁(yè) |
| 文件大小： | 152K |
| 代理商： | S2052 |
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2
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
S2052
April 29, 1999 / Revision E
Internal clocking and control functions are transpar-
ent to the user. Details of data timing can be seen in
Figure 4. A block diagram showing the basic chip
operation is shown in Figure 3.
Loopback
Local loopback is supported by the chip, and pro-
vides a capability for performing offline testing of the
interface to ensure the integrity of the serial channel
before enabling the transmission medium. It also al-
lows for system diagnostics.
S2052 OVERVIEW
The S2052 transmitter and receiver provide serializa-
tion and deserialization functions for block-encoded
data to implement a Fibre Channel interface. Opera-
tion of the S2052 is straightforward, as depicted in
Figure 2. The sequence of operations is as follows:
Transmitter
1. 10-bit parallel input
2. Parallel-to-serial conversion
3. Serial output
Receiver
1. Clock and data recovery from serial input
2. Serial-to-parallel conversion
3. Frame detection
4. 10-bit parallel output
The 10-bit parallel data handled by the S2052 device
should be from a DC-balanced encoding scheme, such
as the 8B/10B transmission code, in which informa-
tion to be transmitted is encoded 8 bits at a time into
10-bit transmission characters
1
, and be compliant with
ANSI X3.230 FC-PH (Fibre Channel Physical and Sig-
naling Interface).
Figure 2. Interface Diagram
Parallel
Data In
S2052
Transceiver
TBC
Serial
Data In
RBC
Parallel
Data Out
COM_DET
Serial
Data Out
TXTESTN
TX [0:9]
10
10
PLL CLOCK
MULTIPLIER
F0 = F1 X 10
SHIFT
REGISTER
TXP
TXN
D
Q
PLL CLOCK
RECOVERY
2:1
D
10
D
BITCLK
Q
COM_DET
DETECT
LOGIC
CONTROL
LOGIC
RXP
RXN
TBC
RXBYPN
TP
TN
EWRAP
-LCK_REF
EN_CDET
RX[0:9]
RBC1
COM_DET
RBC0
SHIFT
REGISTER
Input
Latch
Figure 3. Functional Block Diagram
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