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參數(shù)資料
| 型號： | S2052 |
| 廠商： | APPLIEDMICRO INC |
| 元件分類： | 網絡接口 |
| 英文描述： | Fibre Channel and GigaBit Ethernet Transceiver(用于高速串行數(shù)據傳送的光纖通道和千兆位以太網收發(fā)器) |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 12/15頁 |
| 文件大?。?/td> | 152K |
| 代理商： | S2052 |
12
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
S2052
April 29, 1999 / Revision E
Parameters
Transmitter Output Jitter Allocation
Description
Min
Max
Units
Conditions
T
1
T
2
T
SDR ,
T
SDF
Data setup w.r.t. REFCLK
Data hold w.r.t. REFCLK
Serial data rise and fall
2
1.0
—
—
—
300
ns
ns
ps
See note.
—
20% to 80%, tested on a sample basis.
T
J
Serial data output total
jitter (RMS)
—
192
ps
Peak-to-peak, tested on a sample basis.
Measured with
±
K28.5 or 2
7
-1 pattern.
Measured with K28.5
±
@ 1.25 GHz.
—
80
ps
Peak-to-peak, tested on a sample basis.
Serial data output
deterministic jitter (p-p)
T
DJ
Table 4. S2052 Transmitter Timing
Table 5. S2052 Receiver Timing
Table 3. S2052 Performance Summary
Parameter
Parameters
Description
Min
Max
Units
Conditions
T
3
T
4
T
5
T
6
T
7
T
RCR ,
T
RCF
T
DR ,
T
DF
T
SDR ,
T
SDF
T
LOCK
Duty Cycle
Input Jitter
Tolerance
RBC0 to RBC1 skew
Data setup w.r.t. RBC0, RBC1
Data hold w.r.t. RBC0, RBC1
Data setup w.r.t. RBC0, RBC1
Data hold w.r.t. RBC0, RBC1
RBC0, RBC1 rise and fall time
Data Output rise and fall time
Serial data input rise and fall
Data acquisition lock time @
<1.0625Gb/s
RBC0/RBC1 Duty Cycle
Input data eye opening
allocation at receiver input
for BER
≤
1E–12
—
3.0
1.5
2.5
1.5
—
—
—
—
40%
24%
1
3.0
3.0
300
2.4
60%
—
ns
ns
ns
ns
ns
ns
ns
ps
μ
s
bit time
Tested on a sample basis.
1.0625 GHz Mode
1.0625 GHz Mode
1.250 GHz Mode
1.250 GHz Mode
Measured from .8V to 2.0V.
Measured from .8V to 2.0V.
20% to 80%. (See Figure 10.)
8B/10B IDLE pattern sample basis.
As specified in IEEE 803.3z.
S2052
Units
Operating Frequency *
Serial clock period
Byte clock period
Acquisition Time
Reference clock
1250
.800
8.00
250
125.0
10
1062.5
.941
9.41
250
106.25
Mbit/s
ns
ns
ns
MHz
Word width
*
±
10% lock range, nominal frequency is per FC-PH standard.
10
Bits
Note: All AC measurements are made from the reference voltage level of the clock (1.4V) to the valid input or output data levels
(.8V or 2.0V).
Note: All TTL/CMOS AC measurements are assumed to have the output load of 10pF.
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| S2055AF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:SILICON DIFFUSED POWER TRANSISTOR |
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