參數(shù)資料
型號(hào)： S2053
廠商： APPLIEDMICRO INC
元件分類(lèi)： 網(wǎng)絡(luò)接口
英文描述： Fibre Channel and GigaBit Ethernet Transceiver(用于高速串行數(shù)據(jù)傳送的光纖通道和千兆位以太網(wǎng)收發(fā)器)
中文描述： DATACOM, ETHERNET TRANSCEIVER, PQFP64
封裝： PLASTIC, QFP-64
文件頁(yè)數(shù)： 1/15頁(yè)
文件大?。?/td> 125K
代理商： S2053
1
FIBRE CHANNEL AND GIGABIT ETHERNET TRANSCEIVER
S2053
S2053
FEATURES
Functionally compliant with ANSI X3T11 Fibre
Channel physical and transmission protocol
standards and IEEE 802.3z Gigabit Ethernet
Applications
Transmitter incorporates phase-locked loop
(PLL) providing clock synthesis from low-speed
reference
Receiver PLL configured for clock and data
recovery
1250 and 1062 Mb/s operation
10-bit parallel high drive LVTTL compatible
interface
900mW typical power dissipation
+3.3V power supply
Low-jitter serial LVPECL compatible interface
Lock detect
Local loopback
64 PQFP package
Fibre Channel framing performed by receiver
Continuous downstream clocking from receiver
Drives 30m of Twinax cable directly
Low jitter LVPECL reference clock input option
APPLICATIONS
High-speed data communications
Workstation
Frame buffer
Switched networks
Data broadcast environments
Proprietary extended backplanes
RAID drives
Mass storage devices
GENERAL DESCRIPTION
The S2053 transmitter and receiver chip is designed
to perform high-speed serial data transmission over
fiber optic or coaxial cable interfaces conforming to
the requirements of the ANSI X3T11 Fibre Channel
specification and the IEEE 802.3z Gigabit Ethernet.
The chip runs at 1250.0, and 1062.5 Mbit/s data rates
with associated 10-bit data word.
The S2053 is similar to the AMCC S2052. The S2053
provides the option of either a single ended LVTTL or
a differential LVPECL reference clock input and high
drive LVTTL outputs. The differential LVPECL refer-
ence clock input provides the lowest transmitter output
jitter solution. The high drive LVTTL outputs allow
longer trace lengths or connectors to be used be-
tween the S2053 and the Media Access Controller.
The chip performs parallel-to-serial and serial-to-
parallel conversion and framing for block-encoded
data. The transmitter’s on-chip PLL synthesizes the
high-speed clock from a low-speed reference. The
receiver’s on-chip PLL synchronizes directly to
incoming digital signal to receive the data stream.
The transmitter and receiver each support differential
LVPECL-compatible I/O for fiber optic component
interfaces, to minimize crosstalk and maximize data
integrity. Local loopback mode is provided for system
diagnostics.
Figure 1 shows a typical configuration incorporating
the chip, which is compatible with AMCC’s S2036
Open Fiber Control (OFC) device.
Figure 1. System Block Diagram
PRELIMINARY
DEVICE SPECIFICATION
Optical
TX
Optical
RX
Optical
RX
Optical
TX
S2036
Open Fiber
Control
(OFC)
S2036
Open Fiber
Control
(OFC)
S2053
S2053
Gigabit
Ethernet
Controller
Gigabit
Ethernet
Controller
相關(guān)PDF資料
PDF描述
S2054 Fibre Channel and GigaBit Ethernet Transceiver(帶雙接收和發(fā)送串行I/O的光纖通道和千兆位以太網(wǎng)收發(fā)器)
S2055A SILICON DIFFUSED POWER TRANSISTOR
S2057 Port Bypass Circuit for Fibre Channel and GigaBit Ethernet(用于光纖通道和千兆位以太網(wǎng)的端口旁路電路)
S2058 Port Bypass and Repeater for Fibre Channel Arbitrated Loop(用于光纖通道仲裁環(huán)路的端口旁路電路和中繼器)
S2060 GIGABIT ETHERNET TRANSCEIVER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
S2054AG4 制造商:TYAN 功能描述:M-ATX SOCKET-370 INTEL 810 - Bulk
S2055 制造商:ISC 制造商全稱(chēng):Inchange Semiconductor Company Limited 功能描述:Silicon NPN Power Transistors
S2055A 制造商:SAVANTIC 制造商全稱(chēng):Savantic, Inc. 功能描述:Silicon NPN Power Transistors
S2055AF 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:SILICON DIFFUSED POWER TRANSISTOR
S2055F 制造商:ISC 制造商全稱(chēng):Inchange Semiconductor Company Limited 功能描述:Silicon NPN Power Transistors
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*