參數(shù)資料
型號： S1R72C05B08
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA121
封裝： 8 X 8 MM, 0.65 MM PITCH, PLASTIC, TFBGA-121
文件頁數(shù)： 21/49頁
文件大?。?/td> 545K
代理商： S1R72C05B08
7. ELECTRICAL CHARACTERISTICS
S1R72C05*** Data Sheet (Rev.1.00)
EPSON
23
7.4.3 CPU/DMA I/F Access Timing
7.4.3.1 Specifications for CVDD = 1.65 V to 3.6 V
XDREQ0/1(O)
XDACK0/1(I)
XCS(I)
XRD(I)
CD(O)
Valid
tcas
CA(I)
XWRH/L(I)
XWR
CD(I)
Code
tcas
tccs
Min.
6
Typ.
-
Max.
-
unit
ns
tcch
tcah
6
-
ns
trbd
1
-
ns
trdf
-
35
ns
trdh
3
-
ns
trbh
-
10
ns
twds
twdh
-
6
-
10
-
ns
tdrn
-
35
ns
tdaa
tdan
6
-
ns
tcah
tccs
tcch
trbd
trdf
trdh
trbh
twds
twdh
tdrn
tdaa
tdan
Write
Read
tras
40
-
ns
twas
40
-
ns
twas
trng
twng
twcy
trcy
80
-
ns
trng
25
-
ns
80
-
ns
twcy
25
-
ns
twng
XBEH/L(I)
twbs
twbh
twbs
twbh
6
-
ns
Write byte enable hold time
(CL=30pF)
Item
Address setup time
Address hold time
XCS setup time
XCS hold time
Read data output start time
Read data confirmation time
Read data hold time
Read data output delay time
Write data acknowledge delay time
Write data hold time (after strobe negation)
XDREQ0/1 negate delay time
XDACK0/1 setup time
XDACK0/1 hold time
Read strobe assert time
Write strobe assert time
Read cycle
Read strobe negate time
Write cycle
Write strobe negate time
Write byte enable setup time
twah
50
-
ns
Write data hold time (after strobe assertion)
twah
tccn
15
-
ns
XCS Negate time (Only when CPUIF mode is set*)
* For details of CPUIF mode setting, refer to “Technical Manual.”
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