參數(shù)資料
型號(hào)： S1R72C05B08
元件分類： 總線控制器
英文描述： UNIVERSAL SERIAL BUS CONTROLLER, PBGA121
封裝： 8 X 8 MM, 0.65 MM PITCH, PLASTIC, TFBGA-121
文件頁(yè)數(shù)： 26/49頁(yè)
文件大?。?/td> 545K
代理商： S1R72C05B08
7. ELECTRICAL CHARACTERISTICS
S1R72C05*** Data Sheet (Rev.1.00)
EPSON
27
7.4.4.3 DMA Read Timing
stable
XHCS[1:0](O)
HDA[2:0](O)
HDMARQ(I)
XHDMACK(O)
XHIOR(O)
HDD[15:0](I)
T343
T341
T345
T346
T347
T348
T342
T349
T34a
T344
Code
Description
Min.
Typ.
Max.
Units
T341
70
-
ns
T342
50
-
ns
T343
17
-
ns
T344
0
-
ns
T345
0
-
ns
T346
-
(AP+4) *
16.7 - 3
-
ns
T347
-
(NP+4) *
16.7 + 3
-
ns
T348
30
-
90
ns
T349
10
-
ns
T34a
0
-
ns
Data transfer direction:
S1R72C05
DATA
XHCS
↑, HDA → XHDMACK ↓
Address setup time
XHIOR
↑ → XHCS ↑, HAD
Address hold time
HDMARQ
↑ → XHDMACK ↓
↓ XHDMACK response time
XHIOR
↓ → HDMARQ negate
HDMARQ hold time
XHDMACK
↓ → XHIOR ↓
XHDMACK setup time
XHIOR
↓ → XHIOR ↑
XHIOR assert pulse width
XHIOR
↑ → XHIOR ↓
XHIOR negate pulse width
XHIOR
↑ → XHDMACK ↑
XHDMACK hold time
HDD
→ XHIOR ↑
Data setup time
XHIOR
↑ → HDD
Data bus hold time
*1: AP = IDE_Tmod.AssertPulseWidth, NP = IDE_Tmod.NegatePulseWidth
For detailed information, refer to “IDE Transfer Mode” in the register description.
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