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參數(shù)資料
| 型號： | S1M8657 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | TX IF/BBA WITH AGC |
| 中文描述： | 德克薩斯州中頻/工商管理帶AGC |
| 文件頁數(shù)： | 23/34頁 |
| 文件大?。?/td> | 281K |
| 代理商： | S1M8657 |
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TX IF/BBA WITH AGC
S1M8657
23
Table 5. Enhanced-Mode Input Range Selection
GPADCV[5:2]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Vin(Mid)
1.0V
2.0V
1.5V
1.5V
0.75V
1.5V
1.5V
1.5V
0.5V
1.0V
1.25V
1.5V
2.0V
1.5V
1.75V
2.0V
Input Range
1V
1V
2V
2V
0.5V
2V
2V
2V
1V
2V
0.5V
1V
2V
0.5V
0.5V
0.5V
LSB mV/Step
4
4
8
8
2
8
8
8
4
8
2
4
8
2
2
2
Zin
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
∞
GP-ADC Enhanced Mode inputs are shown in Table 5. The IC input impedance is always kept high to reduce the
loading effect of the input impedance. However, if the external input divider impedance is very large, the
parasitic capacitor cannot charge or discharge quickly enough, generating a high speed conversion error.
Therefore, it is best to use a low resistance at the input terminal. The LSB step is the difference between the
input voltages that generate two codes, respectively. This is shown in Table 5. The GP-ADC needs the clock for
conversion. This clock self-divides and uses TCXO and influences the conversion time. Although a 412kHz clock
was used in S1M8653B, this IC can select from clock speeds between 308kHz – 1.23 MHz, as shown in Table 6,
according to the contents in SPI register GPADC_MODE[6:7]. The recommended clock speed is between
410kHz – 615kHz.
Table 6. GP-ADC Clock Divide Ratio
GPADC_MODE[7:6]
00
01
10
11
Clock Divide Ratio
16
32
48
64
System Clock(TCXO = 19.68MHz)
1.23MHz
615kHz
410kHz
308kHz
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