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參數(shù)資料
| 型號(hào)： | S1M8657 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | TX IF/BBA WITH AGC |
| 中文描述： | 德克薩斯州中頻/工商管理帶AGC |
| 文件頁數(shù)： | 22/34頁 |
| 文件大小： | 281K |
| 代理商： | S1M8657 |
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S1M8657
TX IF/BBA WITH AGC
22
General Purpose ADC Enhanced-Mode Operation Using SPI
(SEN = high, TXMODE_CONT[0] = high)
When SEN = High the SPI BUS can be used. The GP-ADC operates in the basic mode or enhanced mode. If the
TXMODE_CONT[0] is "1", it operates in the enhanced mode and the SPI registers control the input selection,
clock frequency and input range. The basic setting is the Basic Mode.
If TXMODE_CONT[0] = "1" in the basic mode, the GP-ADC operates in the enhanced mode. If all GP-ADC
related controls and input/output function are conducted through the SPI bus, the GP-ADC only outputs the SPI
input/output. GPENA can also drive GP-ADC; in this case, GPDATA and GPCLK are output and save at the
same time in the SPI register, GPADC_RSLT[7:0], except that nothing can be input to the input select pins ,
SMSB/PAON and SLSB/CLK. It's simpler to think that in this mode the SPI registers perform the roles of what the
parallel control pins did in the existing S1M8653B If GPENA and TXMODE_CONT[7] = High, GP-ADC starts the
conversion. Moreover, for a new conversion, GPENA and TXMODE_CONT[7] must be left at Low, and restart
begins at the rising edge of when they become high. While conversion is going on, GP-ADC cannot receive any
signals. GPADC_RSLT[7:0], which has the GP-ADC conversion value, maintains its previous value until the end
of the new conversion.
Table 3. Enhanced-Mode Register Definition
GP MODE
CLOCK Divide Ratio
D7
1
Input Range
D4
1
Input Select
D1
0
GPADC_MODE[7:0]
Default
D6
0
D5
0
D3
0
D2
0
D0
0
Table 4. Enhanced-Mode Analog MUX
GPADC_MODE[1:0]
00
01
Input Select
GPIN1
Reserved
GPADC_MODE[1:0]
10
11
Input Select
GPIN2
GPIN3
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