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參數(shù)資料
| 型號(hào)： | S1D2512X01 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| 中文描述： | 偏轉(zhuǎn)處理器多同步監(jiān)測(cè)儀 |
| 文件頁(yè)數(shù)： | 9/36頁(yè) |
| 文件大?。?/td> | 376K |
| 代理商： | S1D2512X01 |
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2512X01
8
ELECTRICAL CHARACTERISTICS
(V
DD
= 5V, Tamb = 25
°
C)
I
2
C READ/WRITE
(See also I
2
C table control and I
2
C sub address control)
OPERATING CONDITIONS
(V
DD
= 5V, Tamb = 25
°
C)
Table 6. Sync Processor Electrical Characteristics
Parameter
Symbol
VINTH
Conditions
Min
Typ
Max
0.8
Unit
V
V
K
ns
V
V
Horizontal and vertical input threshold
voltage (pin 1, 2)
Low level
High level
Pins 1,2
Pin 3, Cout = 20pF
Locked, I
LOCKOUT
= -250
μ
A
Unlocked, I
LOCKOUT
= +250
μ
A
C0 = 820pF
2.2
Horizontal and vertical pull-up resister
Falling and rising output CMOS buffer
Horizontal 1st PLL lock output status
(pin 3)
RIN
TfrOut
VHlock
200
200
0.5
4.4
0
5
Extracted Vsync integration time (% of
TH
(see 9)
) on H/V composite
VoutT
26
35
%
Table 7. I
2
C Read/Write Operating Conditions
Parameter
Symbol
VinH
VinL
tBUF
Condition
Min
3.0
0
1.3
Typ
-
-
-
Max
5.0
1.5
-
Unit
V
V
μ
s
Input high level voltage
Input low level voltage
Hold time before a new
transmission can start
Hold time for start conditions
Set-up time for stop conditions
Hold time data
Set-up time data
Rise time of SCL
Fall time of SCL
Maximum clock frequency
Low period of the SCL clock
High period of the SCL clock
SDA and SCL input threshold
Acknowledge output voltage on
SDA input with 3mA
tHDS
tSUP
tHDAT
tSUPDAT
tR
tF
Fscl
Tlow
Thigh
Vinth
VACK
0.6
0.6
0.3
0.25
-
-
-
-
-
-
-
-
-
-
-
-
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
kHz
μ
s
μ
s
V
V
1.0
3.0
400
Pin 30
Pin 30
Pin 30
Pin 30, 31
Pin 31
1.3
0.6
2.2
0.4
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