參數(shù)資料
型號(hào)： S1D2512X01
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
中文描述： 偏轉(zhuǎn)處理器多同步監(jiān)測(cè)儀
文件頁(yè)數(shù)： 27/36頁(yè)
文件大?。?/td> 376K
代理商： S1D2512X01
DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2512X01
26
The control voltage of the VCO is typically comprised between 1.33V and 6V (see figure 6). The theoretical
frequency range of this VCO is in the ratio 1 to 4.5, the effective frequency range has to be smaller 1 to 4.2 due to
clamp intervention on filter lowest value. To avoid spread of external components and the circuit itself, it is possible
to adjust free running frequency through I
2
C. This adjustment can be made automatically on the manufacturing line
without manual operation by using lock/unlock information. The adjustment range is 0.8 to 1.3 F0 (where 1.3 F0 is
the free running frequency at power on reset).
The sync frequency has to be always higher than the free running frequency. As an example for a Synchro range
from 24kHz to 100kHz, the suggested free running frequency is 23kHz.
Another feature is the capability for MCU to force horizontal frequency through I
2
C to 2xF0 or 3xF0 (for burn in
mode or safety requirement). In this case, inhibition switch is opened leaving PLL1 free but voltage on PLL1 filter is
forced to 2.66V for 2xF0 or 4.0V for 3xF0.
The PLL1 ensures the coincidence between the leading edge of the Synchro signal and a phase reference
obtained by comparison between the sawtooth of the VCO and an internal DC voltage I
2
C adjustable between
2.8V and 4.0V (corresponding to
±
10%) (see Figure 7)
Figure 6. Details of VCO
Figure 7. PLL1 Timing Diagram
7
6
a
4 I
O
2
I
O
+
-
+
-
6.4V
+
-
RS
Flip
Flop
5
Loop
Filter
(0.80<a<1.30)
I
2
C Free running
Adjustment
I
D
(1.3V < V
7
< 6V)
R0
1.6V
6.4V
1.6V
0.875T
H
0
T
H
Co
H osc
Sawtooth
7/8T
H
1/8T
H
6.4V
2.8V < Vb < 4.0V
Vb
1.6V
Phase REF1
H Synchro
Phase REF1 is obtained by compari-
son between the sawtooth and a DC
voltage adjustable between 2.8V and
4.0V. The PLL1 ensures the exact
coincidence between the signals
phase REF and Hsyns. A
±
T
H
/10
phase adjustment is possible
相關(guān)PDF資料
PDF描述
S1D2512X01-A0B0 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
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