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參數(shù)資料
| 型號： | S1D2512X01 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DEFLECTION PROCESSOR FOR MULTISYNC MONITORS |
| 中文描述： | 偏轉處理器多同步監(jiān)測儀 |
| 文件頁數(shù)： | 17/36頁 |
| 文件大小： | 376K |
| 代理商： | S1D2512X01 |
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DEFLECTION PROCESSOR FOR MULTISYNC MONITORS S1D2512X01
16
NOTES:
1.
2.
3.
4.
Duty cycle is the ratio of power transistor off time period. Power transistor is off when output transistor is off.
Initial condition for safe operation start up.
S and C correction are inhibited so the output sawtooth has a linear shape.
With register 07 at byte x0xxxxxx (s-correction is inhibited) then the S correction is inhibited, and with register 08 at byte
x0xxxxxx (C-Correction is inhibited) consequently the sawtooth has a linear shape.
These parameters are not tested on each unit. They are measured during our internal qualification.
The external power transistor is OFF during 400ns.
These parameters are not tested on each unit. They are measured during out internal qualification.
Refers to notes 4.
TH is the Horizontal period.
10. These parameters are not tested on each unit. They are measured during our internal qualification procedure which
includes characterization on batches coming from corners of our processes and also temperature characterization.
11. See Figure 7 for explanation of reference phase.
12. See Figure 11.
13. This is the frequency range for which the vertical oscillator will automatically synchronize, using a single capacitor value on
Pin 22 and with a constant ramp amplitude.
14. TV is the vertical period.
15. When not used the DC breathing control pin must be connected to 12V.
5.
6.
7.
8.
9.
CAUTIONS:
The ICS near CDT can be latched up by EHT. Therefore, in order to minimize the impact of the EHT, it is necessary to place
ICs far from CDT.
If you have not applied below recommendation, a parasitic effect of ionizing field induced by CDT EHT (Extremely
High Tension) make stock charges between resin and chip surface. In this case, abnormal leakage is increased.
And may cause no operation failure. For protecting CDT’s EHT interference, it is necessary to add metal-sheet for
isolating or locate ICs far from CDT.
Photo#1: Isolation used by metal sheet
Photo#2: Not locate near-by CDT
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