參數(shù)資料
型號(hào)： S1D2512X01
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
中文描述： 偏轉(zhuǎn)處理器多同步監(jiān)測(cè)儀
文件頁(yè)數(shù)： 28/36頁(yè)
文件大?。?/td> 376K
代理商： S1D2512X01
S1D2512X01 DEFLECTION PROCESSOR FOR MULTISYNC MONITORS
27
The S1D2512X01 also includes a lock/unlock identification block which senses in real time whether PLL1 is locked
or not on the incoming horizontal sync signal. The resulting information is available on Hlockout (see sync
processor). The block function is described in figure 5.
When PLL1 is unlocked, It forces Hlockout to leave high.
The lock/unlock information is also available through I
2
C read.
PLL2
The PLL2 ensures a constant position of the shaped Flyback signal in comparison with the sawtooth of the VCO
(Figure 8). The phase comparator of PLL2 (phase type comparator) is followed by a charge pump (typical output
current:0.5mA). The Flyback input is composed of an NPN transistor. This input must be current driven. The
maximum recommended input current is 5mA (see Figure 9).
The duty cycle is adjustable through I
2
C from 30% to 60%. For start up safe operation, initial duty cycle (after
power on reset) is 60% in order to avoid having a too long conduction period of the horizontal scanning transistor.
The maximum storage time (Ts max.) is (0.44T
H
-T
FLY
/2). Typically, T
FLY
/TH is around 20% which means that Ts
max is around 34% of T
H
.
Figure 8. PLL2 Timing Diagram
Figure 9. Flyback Input Electrical Diagram
H osc
Sawtooth
7/8T
H
1/8T
H
6.4V
4.0V
1.6V
Shaped Flyback
H drive
Flyback
Internally
Duty Cycle
Ts
12
HFLY
400
20K
Q1
GND 0V
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