參數(shù)資料
型號: S1C88832F0A0100
元件分類: 微控制器/微處理器
英文描述: MICROCONTROLLER, PQFP128
封裝: PLASTIC, QFP-128
文件頁數(shù): 130/160頁
文件大小: 1244K
代理商: S1C88832F0A0100
S1C88832/88862 TECHNICAL MANUAL
EPSON
63
5 PERIPHERAL CIRCUITS AND THEIR OPERATION (Serial Interface)
Table 5.7.9.1(b) Serial interface control bits
SCS0, SCS1: 00FF48HD3, D4
Select the clock source according to Table 5.7.9.3.
Table 5.7.9.3 Clock source selection
ESIF: 00FF48HD0
Sets the serial interface terminals (P10–P13).
When "1" is written: Serial input/output terminal
When "0" is written: I/O port terminal
Reading:
Valid
The ESIF is the serial interface enable register and
P10–P13 terminals become serial input/output
terminals (SIN, SOUT, SCLK, SRDY) when "1" is
written, and they become I/O port terminals when
"0" is written.
Also, see Table 5.7.3.2 for the terminal settings
according to the transfer modes.
At initial reset, ESIF is set to "0" (I/O port).
SMD0, SMD1: 00FF48HD1, D2
Set the transfer modes according to Table 5.7.9.2.
Table 5.7.9.2 Transfer mode settings
SMD0 and SMD1 can also read out.
At initial reset, this register is set to "0" (clock
synchronous master mode).
SCS0 and SCS1 can also be read out.
In the clock synchronous slave mode, setting of this
register is invalid.
At initial reset, this register is set to "0" (fOSC3/16).
EPR: 00FF48HD6
Selects the parity function.
When "1" is written: With parity
When "0" is written: Non parity
Reading:
Valid
Selects whether or not to check parity of the
received data and to add a parity bit to the trans-
mitting data. When "1" is written to EPR, the most
significant bit of the received data is considered to
be the parity bit and a parity check is executed. A
parity bit is added to the transmitting data. When
"0" is written, neither checking is done nor is a
parity bit added.
Parity is valid only in asynchronous mode and the
EPR setting becomes invalid in the clock synchro-
nous mode.
At initial reset, EPR is set to "0" (non parity).
SMD1
SMD0
Mode
1
0
1
0
1
0
Asynchronous system 8-bit
Asynchronous system 7-bit
Clock synchronous system slave
Clock synchronous system master
SCS1
SCS0
Clock source
1
0
1
0
1
0
Programmable timer
fOSC3 / 4
fOSC3 / 8
fOSC3 / 16
Address Bit
Name
SR R/W
Function
Comment
10
D7
D6
D5
D4
D3
D2
D1
D0
00FF25 D7
D6
D5
D4
D3
D2
D1
D0
FPT1
FPT0
FK1
FK0H
FK0L
FSERR
FSREC
FSTRA
Programmable timer 1 interrupt factor flag
Programmable timer 0 interrupt factor flag
K10 interrupt factor flag
K04–K07 interrupt factor flag
K00–K03 interrupt factor flag
Serial I/F (error) interrupt factor flag
Serial I/F (receiving) interrupt factor flag
Serial I/F (transmitting) interrupt factor flag
0
R/W
(R)
Interrupt
factor is
generated
(W)
Reset
(R)
No interrupt
factor is
generated
(W)
No operation
00FF23
EPT1
EPT0
EK1
EK0H
EK0L
ESERR
ESREC
ESTRA
Programmable timer 1 interrupt enable register
Programmable timer 0 interrupt enable register
K10 interrupt enable register
K04–K07 interrupt enable register
K00–K03 interrupt enable register
Serial I/F (error) interrupt enable register
Serial I/F (receiving) interrupt enable register
Serial I/F (transmitting) interrupt enable register
0
R/W
Interrupt
enable
Interrupt
disable
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