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參數(shù)資料
| 型號： | S-24H30 |
| 廠商： | Seiko Instruments Inc. |
| 英文描述： | 64 Bits Non-Volatile CMOS RAM(64位CMOS非易失性RAM) |
| 中文描述： | 64位非揮發(fā)性CMOS存儲器（64位的CMOS非易失性內(nèi)存） |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 109K |
| 代理商： | S-24H30 |
SERIAL NON-VOLATILE RAM
S-24 Series
6
Seiko Instruments Inc.
Operation
1. Internal latches
The S-24 Series has two latches, one of which controls write operation of the SRAM, and both of which control
permission/inhibition of store operation of the E
2
PROM.
1.1 Previous recall latch
The previous recall latch controls permission/inhibition of store operation of E
2
PROM. It is reset when the power is
turned on, and it inhibits store operation of the E
2
PROM. It is set by executing the software recall instruction or
hardware recall, and it permits store operation of the E
2
PROM.
1.2 Write enable latch
The write enable latch controls permission/inhibition of both store operation of the E
2
PROM and write operation of the
SRAM. It is reset when the power is turned on or by executing WRDS instruction, and it inhibits both store operation of
the E
2
PROM and write operation of the SRAM.
It is set by executing WREN instruction, and it permits both store operation of the E
2
PROM and write operation of the
SRAM.
When store operation of the E
2
PROM is completed, the write enable latch is automatically reset. Therefore, in order to
execute store operation again, it is necessary to execute WREN instruction and to set the write enable latch.
1.3 Both the previous recall latch and the write enable latch must be set for permission of store operation.
2. SRAM mode
2.1 Read
The data is read from the SRAM through READ instruction. Inputting a start bit, address and instruction code causes
data output on DO. In the S-24 Series, a bi-directional serial interface can be made by connecting DI and DO. See
Figures 8 and 9 for the timing.
2.2 Write
The data is written into the SRAM through WRITE instruction. Input data on DI after a start bit, address and instruction
code. See Figures 10 and 11 for the timing. The write enable latch must be set before WRITE instruction.
Figure 7 Internal latch
SRAM
write
operation
control
E
2
PROM
store
operation
control
Set
Reset
Reset
Set
Write enable
latch
Previous
recall
latch
Power-on
Software recall instruction
Hardware recall operation
WREN instruction
Power-on
WRDS instruction
Store operation completed
Set : permission
Reset : inhibition
Set : permission
Reset : inhibition
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| S-24H45I10 | SERIAL NON-VOLATILE RAM |
| S-24H30I10 | CONN DIN PLUG VERT 96POS 3ROWS |
| S-24S30I10 | DIN 41612 PCB Connector; Number of Contacts:96; Number of Rows:3; Pitch Spacing:0.1"; Connector Mounting:PC Board; Contact Termination:Press-Fit; Current Rating:3A; Gender:Male; Leaded Process Compatible:Yes |
| S-24H30IF10 | SERIAL NON-VOLATILE RAM |
| S-24S30IF10 | SERIAL NON-VOLATILE RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| S-24H30I10 | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:SERIAL NON-VOLATILE RAM |
| S-24H30IF10 | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:SERIAL NON-VOLATILE RAM |
| S-24H45 | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:SERIAL NON-VOLATILE RAM |
| S-24H45I10 | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:SERIAL NON-VOLATILE RAM |
| S-24H45IF10 | 制造商:SII 制造商全稱:Seiko Instruments Inc 功能描述:SERIAL NON-VOLATILE RAM |
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