參數(shù)資料
型號: S-24H30
廠商: Seiko Instruments Inc.
英文描述: 64 Bits Non-Volatile CMOS RAM(64位CMOS非易失性RAM)
中文描述: 64位非揮發(fā)性CMOS存儲器(64位的CMOS非易失性內(nèi)存)
文件頁數(shù): 11/16頁
文件大小: 109K
代理商: S-24H30
SERIAL NON-VOLATILE RAM
S-24 Series
10
Seiko Instruments Inc.
Interfacing example 1 : With Intel 8051, 8052
Interfacing example 2 : With other CPU
When the S-24 Series is connected to CPU other than Intel 8051 and 8052, delay circuit should be set by a capacitor and a
resistor at DO terminal (Figure 19), delaying the signal more than 200 ns as in Figure 20 to assure the data hold time (t
DHU
)
and the data setup time (t
DSU
) of CPU.
The maximum speed of the SK clock (f
SKMAX
) is expressed by the following formula:
For example, when interfacing with NEC
μ
PD75XX series, f
SKMAX
is as follows:
8051, 8052
PX.X
P3.1
P3.0
GND
STORE
RECALL
V
CC
DO
CE
SK
DI
Figure 18
Figure 19
200pF
1k
V
CC
CE
SK
DI
DO
STORE
RECALL
GND
CPU
Figure 20
t
DHU
t
PD
SK
DO
(without delay)
DO
(with delay)
t
PD
t
DSU
t
SK
Valid data
Valid data
Valid data
Valid data
t
SK
1
f
SKMAX
=
t
DSU
+t
DHU
+t
PD
max.
=
1
μ
PD75XX series
t
DSU
: 300 ns min.
t
DHU
: 450 ns min.
S-24 Series
t
PD
: 0 ns min. , 300 ns max.
1
×
10
9
t
SK
1
f
SKMAX
=
=
300+450+300
1.05
μ
s
1
=
= 952 kHz
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