參數(shù)資料
型號: S-24H30
廠商: Seiko Instruments Inc.
英文描述: 64 Bits Non-Volatile CMOS RAM(64位CMOS非易失性RAM)
中文描述: 64位非揮發(fā)性CMOS存儲器(64位的CMOS非易失性內(nèi)存)
文件頁數(shù): 10/16頁
文件大?。?/td> 109K
代理商: S-24H30
SERIAL NON-VOLATILE RAM
S-24 Series
Seiko Instruments Inc.
9
Interface with CPU with Serial Port
When SK and DI are high at the rise of CE, high of DI is regarded as a start bit and the clock 1 generates and the high of DI is
fetched. When DI is low, DI is not regarded as a start bit until DI becomes high at the rise of SK.
After power on or after an instruction is performed, DI must be set 1 for preparing the fetch of the start bit of the next
instruction.
Figures 13 to 17 show the timings of write/read, and other operation modes, and interfacing examples are shown in Figures 18 to
20.
Figure 13 Read mode timing(S-24H45, S-24S45)
Figure 14 Read mode timing(S-24H30, S-24S30)
Figure 15 Write mode timing(S-24H45, S-24S45)
Figure 16 Write mode timing(S-24H30, S-24S30)
Figure 17 Other operation mode timing
Execute instruction
Start bit
Dummy bit:
Recommended to be set to 1 for fetching the
start bit of next instruction
Fetch data
CE
SK
DI
8
7
6
5
4
3
2
X
X
X
X
X
I
2
I
1
I
0
~CLK1
9
D15
dummy bit
Fetch CPU data
Start bit
Fetch data
Fetch CPU data
CE
SK
DI
24
23
22
21
20
19
18
17
16
15
14
13
12
11
7
6
5
4
3
A
A
A
~CLK1
A
D0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
D0
Hi-Z
Hi-Z
8
10
25
X
1
1
X
Hi-Z
2
DO
Need not to be fetched
D0
0
Hi-Z
Fetch CPU data
D7
dummy bit
Fetch CPU data
Hi-Z
Start bit
Fetch data
~CLK1
X
X
1
1
X
A
A
A
9
8
7
6
3
4
5
00
2
7
6
5
4
3
1
2
17
16
15
14
11
12
13
10
CE
DI
SK
DO
Need not to be fetched
Dummy bit
Start bit
Fetch data
Write to SRAM
CE
SK
DI
24
25
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
A
A
A
A
X
D0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
1
~CLK1
X
2
Dummy bit
Start bit
Write to SRAM
Fetch data
~CLK1
7
6
5
4
3
2
D0
1
17
16
15
14
11
12
13
00
1
1
0
X
A
A
A
9
8
7
6
3
4
5
CE
DI
SK
相關(guān)PDF資料
PDF描述
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