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參數(shù)資料
| 型號(hào)： | RN5VM112C |
| 廠商： | Ricoh Co., Ltd. |
| 英文描述： | High Speed CMOS Logic Quad D-Type Flip-Flops with 3-State Outputs 16-SO -55 to 125 |
| 中文描述： | 鋰離子電池保護(hù) |
| 文件頁數(shù)： | 15/25頁 |
| 文件大小： | 180K |
| 代理商： | RN5VM112C |
11
RN5VM1
××
C/D
OPERATION
· The VD1 monitors V
DD
pin voltage. When the V
DD
voltage crosses over-charge detector threshold V
DET1
from a low val-
ue to a value higher than the V
DET1
, the VD1 can sense over-charging and an external charge control Nch-MOS-FET
turns to “OFF” with C
OUT
pin being at “L”.
· An output delay time for over-charge detection can be set by an external capacitor C
3
connecting the Vss pin and Ct pin.
The external capacitor can make a delay time from a moment detecting over-charge to a time output a signal which
enables charge control Nch-MOS-FET for turning to “OFF”. Though the V
DD
voltage would be going up to a higher lev-
el than V
DET1
if it is within a time period of the output delay time, VD1 would not output a signal for turning “OFF” of
charg control Nch-MOS-FET. The output delay time can be calculated as below:
t
VDET1
= C
3
×
(V
DD
– 0.7)
0.48
×
10
–6
· A level shifter incorporated in a buffer driver for the C
OUT
pin makes the “L” of C
OUT
pin to the V- pin voltage and the “H”
of C
OUT
pin is set to V
DD
voltage with CMOS buffer.
VD1/Over-Charge Detector
· After detecting over-charge, the VD1 would not be released and C
OUT
level would not switch to “H” again with the excep-
tion that a cell voltage reaches to a lower value than “V
DET1
–V
HYS1
” by self discharge of cell or else. After detecting over-
charge, when the V
DD
level stays at a value higher than “V
DET1
–V
HYS1
”, to connect battery pack to a system load makes
battery pack being disabled at for charging or discharging because of excess current detector operated being D
OUT
“L”.
Reset conditions from overcharging of RN5VM1
××
C
· There can be two cases to reset the VD1 making the C
OUT
pin level to “H” again after detecting over-charge. Resetting
the VD1 makes the charging system ready for resumption of charging process.
The first case is in such condition that a time when the V
DD
voltage is coming down to a level lower than “V
DET1
–V
HYS1
”.
While in the second case, disconnecting a charger from the battery pack can make the VD1 resetting when the V
DD
lev-
el is within hysteresis width (V
DET1
–V
HYS1
≤
V
DD
<V
DET1
)
· After detecting over-charge with the V
DD
voltage of higher than V
DET1
, connecting system load to the battery pack makes
load current allowable through parasitic diode of external charge control Nch-MOS-FET. The C
OUT
level would be “H”
when the V
DD
level is coming down to a level below the V
DET1
by continuous drawing of load current.
Reset conditions from overcharging of RN5VM1
××
D
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RN5VM112C-TR | High Speed CMOS Logic Quad D-Type Flip-Flops with 3-State Outputs 16-TSSOP -55 to 125 |
| RN5VM112D | High Speed CMOS Logic Quad D-Type Flip-Flops with 3-State Outputs 16-TSSOP -55 to 125 |
| RN5VM112D-TR | High Speed CMOS Logic Quad D-Type Flip-Flops with 3-State Outputs 16-TSSOP -55 to 125 |
| RN73C2A115KBTG | RESISTOR SMD 115K |
| RN73C2A118KBTG | RESISTOR SMD 118K |
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