參數(shù)資料
型號(hào)： RM7065A-350T
廠商： PMC-Sierra, Inc.
英文描述： RM7065A⑩ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary
中文描述： RM7065A⑩微處理器與片上二級(jí)高速緩存的數(shù)據(jù)資料的初步
文件頁(yè)數(shù)： 38/52頁(yè)
文件大小： 776K
代理商： RM7065A-350T
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2010145, Issue 2
38
RM7065A
Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
5
Pin Descriptions
The following is a list of control, data, clock, interrupt, and miscellaneous pins of the RM7065A.
Table 17
System Interface
Pin Name
ExtRqst*
Type
Input
Description
External request
Signals that the system interface is submitting an external request.
Release interface
Signals that the processor is releasing the system interface to slave
state
Read Ready
Signals that an external agent can now accept a processor read.
Write Ready
Signals that an external agent can now accept a processor write
request.
Valid Input
Signals that an external agent is now driving a valid address or data on
the SysAD bus and a valid command or data identifier on the SysCmd
bus.
Valid output
Signals that the processor is now driving a valid address or data on the
SysAD bus and a valid command or data identifier on the SysCmd bus.
Processor Request
When asserted this signal requests that control of the system interface
be returned to the processor. This is enabled by Mode Bit 26.
Processor Acknowledge
When asserted, in response to PRqst*, this signal indicates to the
processor that it has been granted control of the system interface.
Response Swap
RspSwap* is used by the external agent to signal the processor when it
is about to return a memory reference out of order; i.e., of two
outstanding memory references, the data for the second reference is
being returned ahead of the data for the first reference. Note that this
signal works as a toggle; i.e., for each cycle that it is held asserted the
order of return is reversed. By default, anytime the processor issues a
second read it is assumed that the reads will be returned in order; i.e.,
no action is required if the reads are indeed returned in order. This is
enabled by Mode Bit 26.
Read Type
During the address cycle of a read request, RdType indicates whether
the read request is an instruction read or a data read.
System address/data bus
A 64-bit address and data bus for communication between the
processor and an external agent.
Release*
Output
RdRdy*
Input
WrRdy*
Input
ValidIn*
Input
ValidOut*
Output
PRqst*
Output
PAck*
Input
RspSwap*
Input
RdType
Output
SysAD(63:0)
Input/Output
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