參數(shù)資料
型號(hào)： RM7065A-350T
廠商： PMC-Sierra, Inc.
英文描述： RM7065A⑩ Microprocessor with On-Chip Secondary Cache Data Sheet Preliminary
中文描述： RM7065A⑩微處理器與片上二級(jí)高速緩存的數(shù)據(jù)資料的初步
文件頁(yè)數(shù)： 35/52頁(yè)
文件大小： 776K
代理商： RM7065A-350T
Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2010145, Issue 2
35
RM7065A
Microprocessor with On-Chip Secondary Cache Data Sheet
Preliminary
Table 11 Cause Register
Table 12 Interrupt Control Register
Table 13 IPLLO Register
Table 14 IPLHI Register
In the IPLLO and IPLHI registers, each interrupt is represented by a four-bit field, thereby
allowing each interrupt to be programmed with a priority level from 0 to 13 inclusive. The
priorities can be set in any manner, including having all the priorities set exactly the same. Priority
0 is the highest level and priority 15 the lowest. The format of the priority level registers is shown
in Table 13 and Table 14 above. The priority level registers are located in the coprocessor 0 control
register space.
In addition to programmable priority levels, the RM7065A also permits the spacing between
interrupt vectors to be programmed. For example, the minimum spacing between two adjacent
vectors is 0x20 while the maximum is 0x200. This programmability allows the user to either set up
the vectors as jumps to the actual interrupt routines or, if interrupt latency is paramount, to include
the entire interrupt routine at one vector. Table 15 illustrates the complete set of vector spacing
selections along with the coding as required in the
Interrupt Control
register
bits 4:0.
In general, the active interrupt priority, combined with the spacing setting, generates a vector offset
which is then added to the interrupt base address of 0x200 to generate the interrupt exception
offset. This offset is then added to the exception base to produce the final interrupt vector address.
31
30
29,28
CE
27
26
25
24
23..8
IP[15..0]
7
6..2
EXC
0,1
BD
0
0
W2
W1
IV
0
0
31..16
15..8
IM[15..8]
7
6..5
4..0
Spacing
0
TE
0
31..28
IPL7
27..24
IPL6
23..20
IPL5
19..16
IPL4
15..12
IPL3
11..8
IPL2
7..4
IPL1
3..0
IPL0
31..28
27..24
23..20
IPL13
19..16
IPL12
15..12
IPL11
11..8
IPL10
7..4
IPL9
3..0
IPL8
0
0
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