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參數(shù)資料
| 型號(hào)： | RM5231-150-Q |
| 廠商： | PMC-SIERRA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RM5231⑩ Microprocessor with 32-Bit System Bus Data Sheet Released |
| 中文描述： | 64-BIT, 150 MHz, MICROPROCESSOR, PQFP128 |
| 封裝： | POWER, QFP-128 |
| 文件頁數(shù)： | 21/39頁 |
| 文件大?。?/td> | 630K |
| 代理商： | RM5231-150-Q |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customer
’
s Internal Use
Document ID: PMC-2002165, Issue 1
21
RM5231
Microprocessor with 32-bit System Bus Data Sheet
Released
significantly increases performance by decoupling the
SysAD
bus transfers from the instruction
execution stream.
3.21 System Interface
The system interface consists of a 32-bit Address/Data bus with 4 parity check bits and a 9-bit
command bus. In addition, there are 6 handshake signals and 6 interrupt inputs. The interface is
capable of transferring data between the processor and memory at a peak rate of 400 MB/sec with
a 100 MHz SysClock.
Figure 6 shows a typical embedded system using the RM5231. In this example, a bank of DRAMs
and a memory controller ASIC share the processor
’
s
SysAD
bus while the memory controller
provides separate ports to a boot ROM and an I/O system.
Figure 6 Typical Embedded System Block Diagram
3.22 System Address/Data Bus
The 32-bit System Address Data (
SysAD
) bus is used to transfer addresses and data between the
RM5231 and the rest of the system. It is protected with a 4-bit parity check bus (
SysADC
).
The system interface is configurable to allow easy interfacing to memory and I/O systems of
varying frequencies. The Block Write data rate, Non-Block Write protocol, and Output Drive
Strength are programmable at Boot time via the
Mode Control
bits. The rate at which the
processor receives data is fully controlled by the external device.
3.23 System Command Bus
The RM5231 interface has a 9-bit System Command (
SysCmd
) bus. The command bus indicates
whether the
SysAD
bus carries address or data information on a per-clock basis. If the
SysAD
carries address, then the SysCmd bus also indicates what type of transaction is to take place (for
example, a read or write). If the
SysAD
carries data, then the
SysCmd
bus also gives information
about the data (for example, this is the last data word transmitted, or the data contains an error).
The
SysCmd
bus is bidirectional to support both processor requests and external requests to the
RM5231. Processor requests are initiated by the RM5231 and responded to by an external device.
External requests are issued by an external device and require the RM5231 to respond.
RM5231
Memory I/O
Controller
Flash/
Boot
Rom
Control
x
x
36
PCI Bus
36
8
23
Latch
DRAM
Address
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| RM5231 | RM5231⑩ Microprocessor with 32-Bit System Bus Data Sheet Released |
| RM5231-200-Q | RM5231⑩ Microprocessor with 32-Bit System Bus Data Sheet Released |
| RM5231-250-Q | RM5231⑩ Microprocessor with 32-Bit System Bus Data Sheet Released |
| RM5231A | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
| RM5231A-250-H | RM5231A⑩ Microprocessor with 32-Bit System Bus Data Sheet Preliminary |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| RM5231-150Q-C001 | 制造商:PMC-Sierra 功能描述: |
| RM5231-200Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5231-225Q | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:64-Bit Microprocessor |
| RM5231-250Q | 制造商:QED 功能描述:Microprocessor, 64 Bit, 128 Pin, Plastic, QFP |
| RM5231A | 制造商:PMC 制造商全稱:PMC 功能描述:64-Bit MIPS RISC Microprocessor with 32/64-Bit System Bus |
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