185
8008H–AVR–04/11
ATtiny48/88
19.1.1
EEPROM Write Prevents Writing to SPMCSR
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
19.1.2
Reading the Fuse and Lock Bits from Software
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the RFLB and SELFPRGEN bits in SPMCSR. When an LPM
instruction is executed within three CPU cycles after the RFLB and SELFPRGEN bits are set in
SPMCSR, the value of the Lock bits will be loaded in the destination register. The RFLB and
SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM instruc-
tion is executed within three CPU cycles or no SPM instruction is executed within four CPU
cycles. When RFLB and SELFPRGEN are cleared, LPM will work as described in the Instruction
set Manual.
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the RFLB and
SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles after
the RFLB and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB)
detailed description and mapping of the Fuse Low byte.
Similarly, when reading the Fuse High byte (FHB), load 0x0003 in the Z-pointer. When an LPM
instruction is executed within three cycles after the RFLB and SELFPRGEN bits are set in the
SPMCSR, the value of the Fuse High byte will be loaded in the destination register as shown
Fuse Extended byte can be read by loading the Z-pointer with 0x0002. When an LPM instruction
is executed within three cycles after the RFLB and SPMEN bits are set in the SPMCSR, the
value of the Fuse Extended Byte (FEB) will be loaded in the destination register as shown
byte.
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
Bit
76543210
Rd
––––––
LB2
LB1
Bit
7
6
5
4
321
0
Rd
FLB7
FLB6
FLB5
FLB4
FLB3
FLB2
FLB1
FLB0
Bit
765
4
321
0
Rd
FHB7
FHB6
FHB5
FHB4
FHB3
FHB2
FHB1
FHB0
Bit
7
6
5
4
321
0
Rd
FEB7
FEB6
FEB5
FEB4
FEB3
FEB2
FEB1
FEB0