15
8008H–AVR–04/11
ATtiny48/88
4.9
Register Description
4.9.1
SPH and SPL — Stack Pointer Registers
Bits 9:0 – SP[10:0]: Stack Pointer
The Stack Pointer register points to the top of the stack, which is implemented growing from
higher memory locations to lower memory locations. Hence, a stack PUSH command decreases
the Stack Pointer.
The stack space in the data SRAM must be defined by the program before any subroutine calls
are executed or interrupts are enabled.
4.9.2
SREG – Status Register
Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-
rupt enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the instruction set reference.
Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-
nation for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful
in BCD arithmetic. See the “Instruction Set Description” for detailed information.
Bit 4 – S: Sign Bit, S = N
⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
Initial Value
000000
RAMEND
Read/Write
RRRRRR
R/W
Bit
151413121110
9
8
–
––––
SP9
SP8
SPH
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
Bit
765
43210
Read/Write
R/W
Initial Value
RAMEND
Bit
7
65
43
21
0
I
T
H
S
V
N
Z
C
SREG
Read/Write
R/W
Initial Value
0