113
8008H–AVR–04/11
ATtiny48/88
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
12.11.3
TCCR1C – Timer/Counter1 Control Register C
Bit 7 – FOC1A: Force Output Compare for Channel A
Bit 6 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM1[3:0] bits specifies a non-PWM mode.
However, for ensuring compatibility with future devices, these bits must be set to zero when
TCCR1A is written when operating in a PWM mode. When writing a logical one to the
FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit.
The OC1A/OC1B output is changed according to its COM1x[1:0] bits setting. Note that the
FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the
COM1x[1:0] bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer
on Compare match (CTC) mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
Bits 5:0 – Res: Reserved Bits
These bits are reserved and will always read zero.
12.11.4
TCNT1H and TCNT1L – Timer/Counter1
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Register
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a com-
pare match between TCNT1 and one of the OCR1x Registers.
10
1
clk
I/O/1024 (From prescaler)
1
0
External clock source on T1 pin. Clock on falling edge.
1
External clock source on T1 pin. Clock on rising edge.
Table 12-6.
Clock Select Bit Description (Continued)
CS12
CS11
CS10
Description
Bit
7
6
5
4
3
2
1
0
FOC1A
FOC1B
–
TCCR1C
Read/Write
R/W
R
Initial Value
0
Bit
7
654
32
10
TCNT1[15:8]
TCNT1H
TCNT1[7:0]
TCNT1L
Read/Write
R/W
Initial Value
0