
Rev. 1.00 Sep. 13, 2007 Page xxvi of xxviii
24.7.3
Setting Oscillation Settling Time after Exit from Software Standby Mode...... 967
24.7.4
Software Standby Mode Application Example................................................. 969
24.8
Deep Software Standby Mode .......................................................................................... 970
24.8.1
Entry to Deep Software Standby Mode ............................................................ 970
24.8.2
Exit from Deep Software Standby Mode.......................................................... 971
24.8.3
Pin State on Exit from Deep Software Standby Mode...................................... 972
24.8.4
B
φ Operation after Exit from Deep Software Standby Mode ........................... 973
24.8.5
Setting Oscillation Settling Time after Exit from Deep Software
Standby Mode ................................................................................................... 974
24.8.6
Deep Software Standby Mode Application Example ....................................... 976
24.8.7
Flowchart of Deep Software Standby Mode Operation .................................... 980
24.9
Hardware Standby Mode .................................................................................................. 982
24.9.1
Transition to Hardware Standby Mode............................................................. 982
24.9.2
Clearing Hardware Standby Mode.................................................................... 982
24.9.3
Hardware Standby Mode Timing...................................................................... 982
24.9.4
Timing Sequence at Power-On ......................................................................... 983
24.10 Sleep Instruction Exception Handling .............................................................................. 984
24.11
Βφ Clock Output Control.................................................................................................. 987
24.12 Usage Notes ...................................................................................................................... 988
24.12.1
I/O Port Status................................................................................................... 988
24.12.2
Current Consumption during Oscillation Settling Standby Period ................... 988
24.12.3
Module Stop State of DMAC or DTC .............................................................. 988
24.12.4
On-Chip Peripheral Module Interrupts ............................................................. 988
24.12.5
Writing to MSTPCRA, MSTPCRB, and MSTPCRC ....................................... 988
24.12.6
Control of Input Buffers by DIRQnE (n = 3 to 0)............................................. 989
24.12.7
Input Buffer Control by DIRQnE (n = 3 to 0) .................................................. 989
24.12.8
B
φ Output State ................................................................................................ 989
Section 25 List of Registers................................................................................. 991
25.1
Register Addresses (Address Order)................................................................................. 992
25.2
Register Bits ................................................................................................................... 1008
25.3
Register States in Each Operating Mode ........................................................................ 1030
Section 26 Electrical Characteristics ................................................................. 1047
26.1
Absolute Maximum Ratings ........................................................................................... 1047
26.2
DC Characteristics .......................................................................................................... 1048
26.3
AC Characteristics .......................................................................................................... 1051
26.3.1
Clock Timing .................................................................................................. 1051
26.3.2
Control Signal Timing .................................................................................... 1054
26.3.3
Bus Timing ..................................................................................................... 1055