
Rev. 1.00 Sep. 13, 2007 Page xxiv of xxviii
Section 21 Flash Memory.................................................................................... 817
21.1
Features............................................................................................................................. 817
21.2
Mode Transition Diagram................................................................................................. 820
21.3
Memory MAT Configuration ........................................................................................... 822
21.4
Block Structure .................................................................................................................823
21.4.1
Block Diagram of H8SX/1642K....................................................................... 823
21.4.2
Block Diagram of H8SX/1644.......................................................................... 824
21.4.3
Block Diagram of H8SX/1648.......................................................................... 825
21.5
Programming/Erasing Interface ........................................................................................ 826
21.6
Input/Output Pins.............................................................................................................. 828
21.7
Register Descriptions........................................................................................................ 828
21.7.1
Programming/Erasing Interface Registers ........................................................ 829
21.7.2
Programming/Erasing Interface Parameters ..................................................... 836
21.7.3
RAM Emulation Register (RAMER)................................................................ 848
21.8
On-Board Programming Mode ......................................................................................... 849
21.8.1
Boot Mode ........................................................................................................ 849
21.8.2
User Program Mode.......................................................................................... 853
21.8.3
User Boot Mode................................................................................................ 863
21.8.4
On-Chip Program and Storable Area for Program Data ................................... 867
21.9
Protection.......................................................................................................................... 873
21.9.1
Hardware Protection ......................................................................................... 873
21.9.2
Software Protection........................................................................................... 874
21.9.3
Error Protection ................................................................................................ 874
21.10 Flash Memory Emulation Using RAM............................................................................. 876
21.11 Switching between User MAT and User Boot MAT........................................................ 879
21.12 Programmer Mode ............................................................................................................ 880
21.13 Standard Serial Communications Interface Specifications for Boot Mode ...................... 880
21.14 Usage Notes ...................................................................................................................... 909
Section 22 Boundary Scan................................................................................... 911
22.1
Features............................................................................................................................. 911
22.2
Block Diagram of Boundary Scan Function ..................................................................... 912
22.3
Input/Output Pins.............................................................................................................. 912
22.4
Register Descriptions........................................................................................................ 913
22.4.1
Instruction Register (JTIR) ............................................................................... 914
22.4.2
Bypass Register (JTBPR) ................................................................................. 915
22.4.3
Boundary Scan Register (JTBSR) .................................................................... 916
22.4.4
IDCODE Register (JTID) ................................................................................. 925
22.5
Operations......................................................................................................................... 926
22.5.1
TAP Controller ................................................................................................. 926