
Rev. 1.00 Sep. 13, 2007 Page xii of xxviii
6.3.7
Software Standby Release IRQ Enable Register (SSIER) ................................ 122
6.4
Interrupt Sources...............................................................................................................123
6.4.1
External Interrupts ............................................................................................ 123
6.4.2
Internal Interrupts ............................................................................................. 124
6.5
Interrupt Exception Handling Vector Table...................................................................... 125
6.6
Interrupt Control Modes and Interrupt Operation............................................................. 131
6.6.1
Interrupt Control Mode 0 .................................................................................. 131
6.6.2
Interrupt Control Mode 2 .................................................................................. 133
6.6.3
Interrupt Exception Handling Sequence ........................................................... 135
6.6.4
Interrupt Response Times ................................................................................. 136
6.6.5
DTC and DMAC Activation by Interrupt ......................................................... 137
6.7
CPU Priority Control Function Over DTC and DMAC.................................................... 140
6.8
Usage Notes ...................................................................................................................... 143
6.8.1
Conflict between Interrupt Generation and Disabling ...................................... 143
6.8.2
Instructions that Disable Interrupts ................................................................... 144
6.8.3
Times when Interrupts are Disabled ................................................................. 144
6.8.4
Interrupts during Execution of EEPMOV Instruction ...................................... 144
6.8.5
Interrupts during Execution of MOVMD and MOVSD Instructions................ 144
6.8.6
Interrupts of Peripheral Modules ...................................................................... 145
Section 7 User Break Controller (UBC).............................................................. 147
7.1
Features............................................................................................................................. 147
7.2
Block Diagram.................................................................................................................. 148
7.3
Register Descriptions........................................................................................................ 149
7.3.1
Break Address Register n (BARA, BARB, BARC, BARD) ............................ 150
7.3.2
Break Address Mask Register n (BAMRA, BAMRB, BAMRC, BAMRD) .... 151
7.3.3
Break Control Register n (BRCRA, BRCRB, BRCRC, BRCRD) ................... 152
7.4
Operation .......................................................................................................................... 154
7.4.1
Setting of Break Control Conditions................................................................. 154
7.4.2
PC Break........................................................................................................... 154
7.4.3
Condition Match Flag ....................................................................................... 155
7.5
Usage Notes ...................................................................................................................... 156
Section 8 Bus Controller (BSC) .......................................................................... 159
8.1
Features............................................................................................................................. 159
8.2
Register Descriptions........................................................................................................ 162
8.2.1
Bus Width Control Register (ABWCR)............................................................ 163
8.2.2
Access State Control Register (ASTCR) .......................................................... 164
8.2.3
Wait Control Registers A and B (WTCRA, WTCRB) ..................................... 165
8.2.4
Read Strobe Timing Control Register (RDNCR) ............................................. 170