
Rev. 1.00 Sep. 13, 2007 Page xviii of xxviii
12.4
Operation .......................................................................................................................... 512
12.4.1
Basic Functions................................................................................................. 512
12.4.2
Synchronous Operation..................................................................................... 518
12.4.3
Buffer Operation ............................................................................................... 520
12.4.4
Cascaded Operation .......................................................................................... 524
12.4.5
PWM Modes..................................................................................................... 526
12.4.6
Phase Counting Mode....................................................................................... 531
12.5
Interrupt Sources...............................................................................................................538
12.6
DTC Activation ................................................................................................................ 540
12.7
DMAC Activation ............................................................................................................ 540
12.8
A/D Converter Activation................................................................................................. 540
12.9
Operation Timing.............................................................................................................. 541
12.9.1
Input/Output Timing ......................................................................................... 541
12.9.2
Interrupt Signal Timing .................................................................................... 545
12.10 Usage Notes ...................................................................................................................... 549
12.10.1
Module Stop Function Setting .......................................................................... 549
12.10.2
Input Clock Restrictions ................................................................................... 549
12.10.3
Caution on Cycle Setting .................................................................................. 550
12.10.4
Conflict between TCNT Write and Clear Operations....................................... 550
12.10.5
Conflict between TCNT Write and Increment Operations ............................... 551
12.10.6
Conflict between TGR Write and Compare Match........................................... 551
12.10.7
Conflict between Buffer Register Write and Compare Match .......................... 552
12.10.8
Conflict between TGR Read and Input Capture ............................................... 552
12.10.9
Conflict between TGR Write and Input Capture .............................................. 553
12.10.10 Conflict between Buffer Register Write and Input Capture.............................. 554
12.10.11 Conflict between Overflow/Underflow and Counter Clearing ......................... 555
12.10.12 Conflict between TCNT Write and Overflow/Underflow ................................ 555
12.10.13 Multiplexing of I/O Pins ................................................................................... 556
12.10.14 PPG1 Setting when TPU1 Pin is Used.............................................................. 556
12.10.15 Interrupts and Module Stop Mode .................................................................... 556
Section 13 Programmable Pulse Generator (PPG) .............................................. 557
13.1
Features............................................................................................................................. 557
13.2
Input/Output Pins.............................................................................................................. 560
13.3
Register Descriptions........................................................................................................ 562
13.3.1
Next Data Enable Registers H, L (NDERH, NDERL) ..................................... 563
13.3.2
Output Data Registers H, L (PODRH, PODRL)............................................... 566
13.3.3
Next Data Registers H, L (NDRH, NDRL) ...................................................... 568
13.3.4
PPG Output Control Register (PCR) ................................................................ 573
13.3.5
PPG Output Mode Register (PMR) .................................................................. 575