
R8C/3JM Group
27. Hardware LIN
R01UH0285EJ0100 Rev.1.00
Aug 08, 2011
27.3.2
LIN Control Register (LINCR)
Notes:
1. After setting the LSTART bit, confirm that the RXDSF flag is set to 1 before Synch Break input starts.
2. Before switching LIN operation modes, stop the LIN operation (LINE bit = 0) once.
3. Inputs to timer RA and UART0 are disabled immediately after the LINE bit is set to 1 (LIN operation starts).
27.3.3
LIN Status Register (LINST)
Address 0106h
Bit
b7b6b5
b4b3b2
b1b0
Symbol
After Reset
000
00
Bit
Symbol
Bit Name
Function
R/W
b0
SFIE
Synch Field measurement-completed
interrupt enable bit
0: Synch Field measurement-completed interrupt
disabled
1: Synch Field measurement-completed interrupt
enabled
R/W
b1
SBIE
Synch Break detection interrupt
enable bit
0: Synch Break detection interrupt disabled
1: Synch Break detection interrupt enabled
R/W
b2
BCIE
Bus collision detection interrupt
enable bit
0: Bus collision detection interrupt disabled
1: Bus collision detection interrupt enabled
R/W
b3
RXDSF RXD0 input status flag
0: RXD0 input enabled
1: RXD0 input disabled
R
b4
LSTART Synch Break detection start bit
(1)When this bit is set to 1, timer RA input is enabled
and RXD0 input is disabled.
When read, the content is 0.
R/W
b5
SBE
RXD0 input unmasking timing
select bit
(effective only in slave mode)
0: Unmasked after Synch Break detected
1: Unmasked after Synch Field measurement
completed
R/W
b6
MST
LIN operation mode setting bit
(2)0: Slave mode
(Synch Break detection circuit operation)
1: Master mode
(timer RA output OR’ed with TXD0)
R/W
b7
LINE
LIN operation start bit
0: LIN operation stops
1: LIN operation starts
(3)R/W
Address 0107h
Bit
b7b6b5
b4b3b2
b1b0
Symbol
After Reset
000
00
Bit
Symbol
Bit Name
Function
R/W
b0
SFDCT Synch Field measurement-completed
flag
When this bit is set to 1, Synch Field measurement
is completed.
R
b1
SBDCT Synch Break detection flag
when this bit is set to 1, Synch Break is detected or
Synch Break generation is completed.
R
b2
BCDCT Bus collision detection flag
When this bit is set to 1, bus collision is detected.
R
b3
B0CLR
SFDCT bit clear bit
When this bit is set to 1, the SFDCT bit is set to 0.
When read, the content is 0.
R/W
b4
B1CLR
SBDCT bit clear bit
When this bit is set to 1, the SBDCT bit is set to 0.
When read, the content is 0.
R/W
b5
B2CLR
BCDCT bit clear bit
When this bit is set to 1, the BCDCT bit is set to 0.
When read, the content is 0.
R/W
b6
—
Nothing is assigned. If necessary, set to 0. When read, the content is 0.
—
b7
—