
R8C/3JM Group
15. DTC
R01UH0285EJ0100 Rev.1.00
Aug 08, 2011
15.3.6
Chain Transfers
When the CHNE bit in the DTCCRj (j = 0 to 22) register is 1 (chain transfers enabled), multiple data transfers
When the DTC is activated, one control data is selected according to the data read from the DTC vector address
corresponding to the activation source, and the selected control data is read from the DTC control data area.
When the CHNE bit for the control data is 1 (chain transfers enabled), the next control data immediately
following the current control data is read and transferred after the current transfer is completed. This operation
is repeated until the data transfer with the control data for which the CHNE bit is 0 (chain transfers disabled) is
completed.
When performing chain transfers using several control data, the number of transfers set to the first control data
is enabled and the number of transfers proceeded after the first control data is disabled.
Set the CHNE bit in the DTCCR23 register to 0 (chain transfers disabled).
Figure 15.10
Flow of Chain Transfers
15.3.7
Interrupt Sources
When the data transfer causing the DTCCTj (j = 0 to 23) register value to change to 0 is performed in normal
mode, and when the data transfer causing the DTCCTj register value to change to 0 is performed while the
RPTINT bit in the DTCCRj register is 1 (interrupt generation enabled) in repeat mode, the interrupt request
corresponding to the activation source is generated for the CPU during DTC operation. However, no interrupt
request is generated for the CPU when the activation source is SSU/I2C bus transmit data empty or flash ready
status.
Interrupt requests for the CPU are affected by the I flag or interrupt control register. In chain transfers, whether
the interrupt request is generated or not is determined either by the number of transfer times specified for the
first type of the transfer or the RPTINT bit. When an interrupt request is generated for the CPU, the bit among
bits DTCENi0 to DTCENi7 in the DTCENi (i = 0 to 6) registers corresponding to the activation source are set
to 0 (activation disabled).
DTC activation source
generation
Read DTC vector
Read control data 1
Transfer data
Write back control data 1
Read control data 2
Data transfer
Write back control data 2
End of DTC transfers
Control data 1
CHNE = 1
Control data 2
CHNE = 0
DTC control data area
CHNE: Bit in DTCCRj register