
R8C/3JM Group
23. Serial Interface (UART2)
R01UH0285EJ0100 Rev.1.00
Aug 08, 2011
23.3
Clock Synchronous Serial I/O Mode
In clock synchronous serial I/O mode, data is transmitted and received using a transfer clock.
Notes:
1. When an external clock is selected, the requirements must be met in either of the following states:
- The external clock is held high when the CKPOL bit in the U2C0 register is set to 0 (transmit data output
at the falling edge and receive data input at the rising edge of the transfer clock)
- The external clock is held low when the CKPOL bit in the U2C0 register is set to 1 (transmit data output
at the rising edge and receive data input at the falling edge of the transfer clock)
2. If an overrun error occurs, the receive data in the U2RB register will be undefined. The IR bit in the S2RIC
register does not change to 1 (interrupt requested).
Table 23.2
Clock Synchronous Serial I/O Mode Specifications
Item
Specification
Transfer data format
Transfer data length: 8 bits
Transfer clock
The CKDIR bit in the U2MR register is set to 0 (internal clock): fj/(2(n+1))
fj = f1, f8, f32, fC n = setting value in the U2BRG register: 00h to FFh
The CKDIR bit is set to 1 (external clock): Input from the CLK2 pin
Transmit/receive control
Selectable from the CTS function, RTS function, or CTS/RTS function disabled.
Transmit start conditions
To start transmission, the following requirements must be met:
(1) The TE bit in the U2C1 register is set to 1 (transmission enabled)
The TI bit in the U2C1 register is set to 0 (data present in the U2TB register)
If the CTS function is selected, input to the CTS2 pin = “L”.
Receive start conditions
To start reception, the following requirements must be met:
(1) The RE bit in the U2C1 register is set to 1 (reception enabled).
The TE bit in the U2C1 register is set to 1 (transmission enabled).
The TI bit in the U2C1 register is set to 0 (data present in the U2TB register).
Interrupt request generation
timing
For transmission, one of the following conditions can be selected.
The U2IRS bit in the U2C1 register is set to 0 (transmit buffer empty):
When data is transferred from the U2TB register to the UART2 transmit register
(at start of transmission).
The U2IRS bit is set to 1 (transmission completed):
When data transmission from the UART2 transmit register is completed.
For reception
When data is transferred from the UART2 receive register to the U2RB register
(at completion of reception).
Error detection
This error occurs if the serial interface starts receiving the next unit of data before
reading the U2RB register and receives the 7th bit of the next unit of data.
Selectable functions
CLK polarity selection
Transfer data I/O can be selected to occur synchronously with the rising or falling
edge of the transfer clock.
LSB first, MSB first selection
Whether transmitting or receiving data begins with bit 0 or begins with bit 7 can be
selected.
Continuous receive mode selection
Reception is enabled immediately by reading the U2RB register.
Serial data logic switching
This function inverts the logic value of the transmit/receive data.