
R8C/36T-A Group
11. Interrupts
Under development Preliminary document
Specifications in this document are tentative and subject to change.
R01UH0240EJ0010 Rev.0.10
Page 128 of 728
Aug 05, 2011
11.1.2
Software Interrupts
A software interrupt is generated when an instruction is executed. Software interrupts are non-maskable.
11.1.2.1
Undefined Instruction Interrupt
An unidentified instruction interrupt is generated when the UND instruction is executed.
11.1.2.2
Overflow Interrupt
An overflow interrupt is generated when the O flag is 1 (arithmetic operation overflow) and the INTO
instruction is executed. Instructions that change the O flag are as follows:
ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, and SUB.
11.1.2.3
BRK Interrupt
A BRK interrupt is generated when the BRK instruction is executed.
11.1.2.4
INT Instruction Interrupt
An INT instruction interrupt is generated when the INT instruction is executed. Software interrupt numbers the
INT instruction can specify are 0 to 63. The number is assigned to each peripheral function interrupt. When the
INT instruction is executed specifying the number, the peripheral function interrupt with the same number can
be executed.
For software interrupt numbers 0 to 31, the U flag in the FLG register is saved on the stack during instruction
execution, and the U flag is set to 0 (ISP selected) before the interrupt sequence is executed. The U flag is
restored from the stack when the MCU returns from the interrupt routine. For software interrupt numbers 32 to
63, the U flag does not change state during instruction execution, and the selected SP is used.
11.1.3
Special Interrupts
Special interrupts are non-maskable.
11.1.3.1
Watchdog Timer Interrupt
This interrupt is generated by the watchdog timer.
11.1.3.2
Oscillation Stop Detection Interrupt
This interrupt is generated by the oscillation stop detection function.
11.1.3.3
Voltage Monitor 1 Interrupt
This interrupt is generated by the voltage detection circuit. A non-maskable or maskable interrupt can be
selected by IRQ1SEL bit in the CMPA register.
11.1.3.4
Voltage Monitor 2 Interrupt
This interrupt is generated by the voltage detection circuit. A non-maskable or maskable interrupt can be
selected by IRQ2SEL bit in the CMPA register.
11.1.3.5
Single-Step Interrupt, Address Break Interrupt
Do not use these interrupts. They are provided exclusively for use in development tools.