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參數(shù)資料
| 型號(hào)： | R5F212ACSNFA |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PQFP48 |
| 封裝： | 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-48 |
| 文件頁數(shù)： | 33/138頁 |
| 文件大?。?/td> | 492K |
| 代理商： | R5F212ACSNFA |
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4317K–AVR–03/2013
AT90PWM2/3/2B/3B
19.3.3.2
Manchester decoder
When configured in Manchester mode, the EUSART receiver is able to receive serial frame
using a 17-bit shift register, an edge detector and several data/control registers. The Manchester
decoder receives a frame from the RxD pin of the EUSART interface and loads the received
data in the EUSART data register (UDR and EUDR).
The bit order of the data bits in the frame is configurable to handle MSB or LSB first.
The polarity of the bi-phase start is not configurable. The start bit a logical ‘1’ (rising edge at bit
center).
The polarity of the stop bits is not configurable, the interface allows to read the 2 stops bits value
by software.
The Manchester decoder is enable when the EUSART is configured in Manchester mode and
the RXEN of USCRB set (global USART receive enable).
The number of data bits to be received can be configured with the URxS bits of EUCSRA
register.
The Manchester decoder provides a special mode where 16 or 17 data bits can be received. In
this mode the Manchester decoder can automatically detects if the seventeenth bit is Manches-
ter encoded or not (seventeenth data bit or first stop bit). If the receiver detects a valid data bit
(Manchester transition) during the seventeenth bit time of the frame, the receiver will process the
frame as a 17-bit frame lenght and set the F1617 bit of EUCSRC register.
In Manchester mode, the clock used for sampling the EUSART input signal is programmed by
the baudrate generator.
The edge detector of the Manchester decoder is based upon a 16 bits up/down counter which
maximum value can be configured through the MUBRRH and MUBRRL registers.
The maximum counter value is given by the following formula:
MUBRR[H:L]=F
CLKIO / (baud rate frequency)
MBURR[H:L] is used to calibrate the detect window of the start bit and to detect time overflow of
the other bits.
19.3.4
Double Speed Operation (U2X)
Double Speed Operation is controlled by U2X bit in UCSRA. See “Double Speed Operation
This mode of operation is not allowed in manchester bit coding.
Each ‘bit time’ in the Manchester serial frame is divided into two phases (See Figure 19-4). The
counter counts during the first phase and counts down during the second one. When the data bit
transition is detected, the counter memorises the N1 counter value and start counting down.
When the counter reaches the zero value, it starts counting up again and the N1/2 value allows
to open the next detection window. This detection window defines the time zone where the next
data bit edge is sampled.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| R5F212ACSNFA#U0 | 制造商:Renesas Electronics Corporation 功能描述:MCU 16-bit R8C CISC 128KB Flash 2.5V/3.3V/5V 64-Pin LQFP 制造商:Renesas Electronics Corporation 功能描述:IC MCU 16BIT 128KB FLASH 64LQFP |
| R5F212ACSNFA#V0 | 功能描述:MCU FLASH 128KB 64-LQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:R8C/2x/2A 標(biāo)準(zhǔn)包裝:96 系列:PIC® 16F 核心處理器:PIC 芯體尺寸:8-位 速度:20MHz 連通性:I²C，SPI 外圍設(shè)備:欠壓檢測(cè)/復(fù)位，POR，PWM，WDT 輸入/輸出數(shù):11 程序存儲(chǔ)器容量:3.5KB（2K x 14） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:128 x 8 電壓 - 電源 (Vcc/Vdd):2.3 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:A/D 8x10b 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 125°C 封裝/外殼:14-TSSOP（0.173"，4.40mm 寬） 包裝:管件 |
| R5F212ACSNFA#V2 | 制造商:Renesas Electronics Corporation 功能描述:R8C/2A 128K/7.5K 64LQFP 14X14 - Trays 制造商:Renesas Electronics Corporation 功能描述:IC MCU 16BIT 128KB FLASH |
| R5F212ACSNFP | 制造商:Renesas Electronics Corporation 功能描述:Microcontroller,R8C/2A,ROM128K |
| R5F212ACSNFP#U0 | 制造商:Renesas Electronics Corporation 功能描述:MCU 16-Bit R8C CISC 128KB Flash 2.5V/3.3V/5V 64-Pin LQFP 制造商:Renesas Electronics Corporation 功能描述:MCU 16BIT R8C CISC 128KB FLASH 2.5V/3.3V/5V 64LQFP - Trays 制造商:Renesas Electronics 功能描述:R8C 20MHz 制造商:Renesas 功能描述:MCU 16-Bit R8C CISC 128KB Flash 2.5V/3.3V/5V 64-Pin LQFP |
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