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參數(shù)資料
| 型號： | R2A20111SPW0 |
| 廠商： | Renesas Technology Corp. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Power Factor Correction Controller IC |
| 中文描述： | 功率因數(shù)校正控制芯片 |
| 文件頁數(shù)： | 34/41頁 |
| 文件大?。?/td> | 310K |
| 代理商： | R2A20111SPW0 |
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R2A20111SP/DD
REJ03F0231-0100 Rev.1.00 Mar 28, 2007
Page 34 of 40
2-2. On/Off Operation by Using the SS Pin
When the voltage on the SS pin is pulled up to the VREF voltage level, the voltage level of the CAO pin is also pulled
up together with the SS pin. Then, the OUT pin is stopped.
After the voltage level of the SS pin is pulled up, a few pulses on the OUT pin may be generated by capacitance of the
phase-compensation circuit of the CAO pin (see figure 19).
The circuit to directly pulls up the CAO pin is not recommended since the circuit may affect the phase-compensation
circuit of the current amplifier.
SS pin voltage
CAO pin voltage
OUT pin voltage
Figure 19 On/Off Operation by Pulling up SS Pin
2-3. On/Off Operation by using the CLIMIT Pin
When the voltage on the CLIMIT pin falls to 1.3 V or lower, the pulses on the OUT pin stop by the overcurrent
detection circuit. When the voltage of the CLIMIT pin is released, the pulses on the OUT pin is resumed without soft
start.
2-4. On/Off Operation by Using the DELAY Pin
When the voltage on the DELAY pin is pulled up to 4 V or more, the IC enters the shutdown state and the pulses on the
OUT pin is stopped. Since the shutdown function is operated in latch mode, the IC is not resumed even when the
voltage level of the DELAY pin is pulled down. The IC resumes only when lower the voltage on the VCC pin to 4 V or
lower once and raise the voltage on the VCC pin higher than the UVL voltage.
Figure 20 illustrates an example of detection circuit.
VREF
PFC output voltage
DELAY pin
1
2
4
3
5
M51958BL
GND
Figure 20 Example of Shutdown Circuit
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