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參數(shù)資料
| 型號： | QL6250E-8PS484M |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 960 CLBS, 248160 GATES, PBGA484 |
| 封裝： | 23 X 23 MM, 1 MM PITCH, MS-034AAJ-1, PLASTIC, BGA-484 |
| 文件頁數(shù)： | 5/64頁 |
| 文件大?。?/td> | 850K |
| 代理商： | QL6250E-8PS484M |
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2006 QuickLogic Corporation
Eclipse-E Family Data Sheet Rev. A
13
Dedicated Clock
There is one dedicated clock in the Eclipse-E Family (QL6250E and QL6325E). This clock connects to the
clock input of the Logic Cell and I/O registers, and RAM blocks through a hardwired connection and is
multiplexed with the programmable clock input. The dedicated clock provides a fast global network with low
skew. Users have the ability to select either the dedicated clock or the programmable clock (Figure 12).
Figure 12: Dedicated Clock Circuitry within Logic Cell
NOTE: For more information on the clocking capabilities of Eclipse-E FPGAs, see QuickLogic Application
Note 68 at http://www.quicklogic.com/images/appnote68.pdf.
I/O Control and Local Hi-Drives
Each bank of I/Os has two input-only pins that can be programmed to drive the RST, CLK, and EN inputs of
I/Os in that bank. These input-only pins also serve as high drive inputs to a quadrant. These buffers can be
driven by the internal logic both as an I/O control or high drive. For I/O constrained designs, these pins can
be used for general purpose inputs. The performance of these resources is presented in Table 8.
Table 9 shows the total number of I/O control pins per device/package combination.
Table 8: I/O Control Network/Local High-Drive
Destination
TT, 25 C, 2.5 V
From Pad
From Array
I/O (far)
1.00 ns
1.14 ns
I/O (near)
0.63 ns
0.78 ns
Skew
0.37 ns
0.36 ns
Table 9: I/O Control Pins per Device/Package Combination
Device
208 PQFP
280 LFBGA
484 BGA
QL6250E
161616
QL6325E
16
Programmable Clock or
General Routing
Dedicated Clock
CLK
Logic Cell
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