參數(shù)資料
型號(hào)： QL6250E-8PS484M
廠(chǎng)商： QUICKLOGIC CORP
元件分類(lèi)： FPGA
英文描述： FPGA, 960 CLBS, 248160 GATES, PBGA484
封裝： 23 X 23 MM, 1 MM PITCH, MS-034AAJ-1, PLASTIC, BGA-484
文件頁(yè)數(shù)： 36/64頁(yè)
文件大?。?/td> 850K
代理商： QL6250E-8PS484M
2006 QuickLogic Corporation
Eclipse-E Family Data Sheet Rev. A
41
PT280 and PS484 Pin Descriptions
Table 26: PT280 and PS484 Pin Descriptions
Pin
Directio
n
Function
Description
JTAG Pin Descriptions
TDI/RSI
I
Test Data In for JTAG/RAM init.
Serial Data In
Hold HIGH during normal operation. Connects to serial
PROM data in for RAM initialization. Connect to VDED2 if
unused
TRSTB/RRO
I/0
Active low Reset for JTAG/RAM
init. reset out
Hold LOW during normal operation. Connects to serial
PROM reset for RAM initialization. Connect to GND if
unused
TMS
I
Test Mode Select for JTAG
Hold HIGH during normal operation. Connect to VDED2 if
not used for JTAG
TCK
I
Test Clock for JTAG
Hold HIGH or LOW during normal operation. Connect to
VDED2 or GND if not used for JTAG
TDO/RCO
O
Test data out for JTAG/RAM init.
clock out
Connect to serial PROM clock for RAM initialization. Must be
left unconnected if not used for JTAG or RAM initialization.
The output voltage drive is specified by VCCIO(C).
Dedicated Pin Descriptions
CLK
I
Global clock network pin
Low skew global clock. This pin provides access to a
dedicated, distributed network capable of driving the
CLOCK, SET, RESET, F1, and A2 inputs to the Logic Cell,
READ, and WRITE CLOCKS, Read and Write Enables of
the Embedded RAM Blocks, CLOCK of the ECUs, and
Output Enables of the I/Os. The voltage tolerance of this pin
is specified by VCCIO(C).
DEDCLK
I
Dedicated clock pin
Very low skew global clock. This pin provides access to a
dedicated, distributed clock network capable of driving the
CLOCK inputs of all sequential elements of the device (e.g.,
RAM, Flip Flops). The voltage tolerance of this pin is
specified by VCCIO(C).
GND
I
Ground pin
Connect to ground.
GNDPLL
I
Ground pin for PLL
Connect to GND.
INREF(A)
I
Differential reference voltage
The INREF is the reference voltage pin for GTL+, SSTL2,
and STTL3 standards. Follow the recommendations
provided in
Table 13 for the appropriate standard. The A
inside the parenthesis means that INREF is located in BANK
A. This pin should be tied to GND if voltage referenced
standards are not used.
I/O(A)
I/O
Input/Output pin
The I/O pin is a bi-directional pin, configurable to either an
input-only, output-only, or bi-directional pin. The A inside the
parenthesis means that the I/O is located in Bank A. If an I/O
is not used, SpDE (QuickWorks Tool) provides the option of
tying that pin to GND, VCC
, or TriState.
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