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參數(shù)資料
| 型號： | QL5232-33APB456I |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA456 |
| 封裝： | PLASTIC, BGA-456 |
| 文件頁數(shù)： | 8/21頁 |
| 文件大小： | 385K |
| 代理商： | QL5232-33APB456I |
68
Preliminary
QL5232 - QuickPCITM
3-68
AC CHARACTERISTICS at VCC = 3.3V, TA = 25
°C (K = 1.00)
(To calculate delays, multiply the appropriate K factor in the “Operating Range” section by the following numbers.)
Logic Cells
RAM Cell Synchronous Write Timing
Notes:
[4] Stated timing for worst case Propagation Delay over process variation at VCC=3.3V and TA=25
°C. Multiply by
the appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating
Range.
[5] These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell
including typical net delays. Worst case delay values for specific paths should be determined from timing analy-
sis of your particular design.
Symbol
Parameter
Propagation Delays (ns)
Fanout [5]
1234
8
tPD
Combinatorial Delay [6]
1.4
1.7
1.9
2.2
3.2
tSU
Setup Time [6]
1.7
tH
Hold Time
0.0
tCLK
Clock to Q Delay
0.7
1.0
1.2
1.5
2.5
tCWHI
Clock High Time
1.2
tCWLO
Clock Low Time
1.2
tSET
Set Delay
1.0
1.3
1.5
1.8
2.8
tRESET
Reset Delay
0.8
1.1
1.3
1.6
2.6
tSW
Set Width
1.9
tRW
Reset Width
1.8
Symbol
Parameter
Propagation Delays (ns)
Fanout [4]
12
34
8
TSWA
WA Setup Time to WCLK
1.0
THWA
WA Hold Time to WCLK
0.0
TSWD
WD Setup Time to WCLK
1.0
THWD
WD Hold Time to WCLK
0.0
TSWE
WE Setup Time to WCLK
1.0
THWE
WE Hold Time to WCLK
0.0
TWCRD
WCLK to RD (WA=RA) [4]
5.0
5.3
5.6
5.9
7.1
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