參數(shù)資料
型號(hào)： QL5232-33APB456I
廠商： QUICKLOGIC CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA456
封裝： PLASTIC, BGA-456
文件頁(yè)數(shù)： 1/21頁(yè)
文件大?。?/td> 385K
代理商： QL5232-33APB456I
3-53
33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and dual Port SRAM
QL5232 - QuickPCITM
Rev B
QL5232 - QuickPCI
Device Highlights
High Performance PCI Controller
s
32-bit / 33 MHz PCI Master/Target
s
Zero-wait state PCI Master provides 132 MB/s transfer rates
s
Programmable back-end interface to optional local processor
s
Independent PCI bus (33 MHz) and local bus
(up to 160 MHz) clocks
s
Fully customizable PCI Configuration Space
s
Configurable FIFOs with depths up to 256
s
Reference design with driver code (Win 95/98/Win 2000/
NT4.0) available
s
PCI v2.2 compliant
s
Supports Type 0 Configuration Cycles in Target mode
s
3.3V, 5V Tolerant PCI signaling supports Universal
PCI Adapter designs
s
3.3V CMOS in 208-pin PQFP and 456-pin PBGA
s
Supports endian conversions
s
Unlimited/Continuous Burst Transfers Supported
Extendable PCI Functionality
s
Support for Configuration Space from 0x40 to 0x3FF
s
Multi-Function, Expanded Capabilities, & Expansion ROM
capable
s
Power management, Compact PCI, hot-swap/hot-plug
compatible
s
PCI v2.2 Power Management Spec compatible
s
PCI v2.2 Vital Product Data (VPD) configuration support
s
Programmable Interrupt Generator
s
I2O support with local processor
s
Mailbox register support
Programmable Logic
s
122K system gates / 1302 Logic Cells
s
25,344 RAM bits, up to 266 I/O pins
s
250 MHz 16-bit counters, 275 MHz Datapaths, 160 MHz FIFOs
s
All back-end interface and glue-logic can be implemented on chip
s
11 64-deep FIFOs or 5 128-deep FIFOs or a 2 256-deep FIFO
or a combination that requires 22 or less QuickLogic RAM
Modules
s
(3) 32-bit busses interface between the PCI Controller and the
Programmable Logic
DEVICE HIGHLIGHTS
FIGURE 1. QL5232 Diagram
Architecture Overview
The QL5232 device in the QuickLogic QuickPCI ESP
(Embedded Standard Product) family provides a
complete and customizable PCI interface solution
combined with 122,000 system gates of
programmable logic. This device eliminates any need
for the designer to worry about PCI bus compliance,
yet allows for the maximum 32-bit PCI bus bandwidth
(132 MB/s).
The programmable logic portion of the device
contains 1302 QuickLogic Logic Cells, and 22
QuickLogic Dual-Port RAM Blocks. These
configurable RAM blocks can be configured in many
width/depth combinations. They can also be
combined with logic cells to form FIFOs, or be
initialized via Serial EEPROM on power-up and used
as ROMs.
The QL5232 device meets PCI 2.2 electrical and
timing specifications and has been fully hardware-
tested. This device also supports the Win’98 and
PC’98 standards. The QL5232 device features 3.3-
volt operation with multi-volt compatible I/Os. Thus it
can easily operate in 3-volt systems and is fully
compatible with 3.3V,5V or Universal PCI card
development.
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ARCHITECTURE OVERVIEW
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