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參數(shù)資料
| 型號： | QL5842-66CPTN280C |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA280 |
| 封裝： | 17 X 17 MM, 1.50 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MO-205, LFBGA-280 |
| 文件頁數(shù)： | 1/76頁 |
| 文件大?。?/td> | 1409K |
| 代理商： | QL5842-66CPTN280C |
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2006 QuickLogic Corporation
1
Device Highlights
High Performance PCI Controller
33/66 MHz 32-bit PCI Master/Target
Zero-wait state PCI Master provides up to
264 MBps transfer rates
Zero-wait-state PCI Target Write/One-wait-state
PCI Target Read interface
Supports all PCI commands, including
configuration and MWI
Supports fully-customizable byte enable for
master channels
Target interface supports retry, disconnect
with/without data transfer, and target abort
Fully programmable back-end interface
Independent PCI bus (33/66 MHz) and local bus
(up to 160 MHz) clocks
Fully customizable PCI Configuration Space
Configurable FIFOs with depths up to 256 words
Reference design with driver code
(Win 95/98/2000/NT 4.0) available
PCI v2.3 compliant
Supports Type 0 Configuration Cycles in Target
mode
3.3 V PCI signaling
1.8 V supply voltage
484-ball PBGA, 280-ball LFBGA, 208-pin PQFP,
196-ball TFBGA, and 144-pin TQFP packages
Supports Extendable PCI functionality
Unlimited/Continuous Burst Transfers supported
Extendable PCI Functionality
Support for Configuration Space from 0
× 40
to 0
× 3FF
PCI v2.3 Power Management Spec. compatible
Multi-function, expanded capabilities, and
expansion ROM capable
PCI v2.3 Vital Product Data (VPD) configuration
support
Flexible Programmable Logic
Up to 1,348 logic cells
Up to 50,688 RAM bits
Up to 262 I/O pins
All back-end interface and glue-logic can be
implemented on chip
Six 32-bit busses interface between the PCI
Controller and the Programmable Logic
Up to twenty-two 2,304 bit dual-port high
performance SRAM blocks
Up to 3,482 flip-flops available
Figure 1: QL58x2 Block Diagram
Parity
Check
Parity
Gen
DMA
Control
FIFO
Target
Control
PCI Bus 33 MHz/32-Bit Address and Data
XY User I/O for Flexible Local Bus
FIFO
User
Defined
Registers
Master
Control
Mux
Configuration
Space
Fixed
PCI Core
32-Bit Interface
Mux
Programmable
Logic
33/66 MHz/32-bit PCI Master/Target with Embedded Programmable
Logic, Embedded Computational Units, and Dual Port SRAM
QL58x2 Enhanced QuickPCI
Family Data Sheet
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