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參數(shù)資料
| 型號： | QL5842-66CPTN280C |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA280 |
| 封裝： | 17 X 17 MM, 1.50 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, PLASTIC, MO-205, LFBGA-280 |
| 文件頁數(shù)： | 5/76頁 |
| 文件大?。?/td> | 1409K |
| 代理商： | QL5842-66CPTN280C |
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2006 QuickLogic Corporation
QL58x2 Enhanced QuickPCI Family Data Sheet Rev. K
13
Embedded Computational Unit (ECU)
Traditional Programmable Logic architectures do not implement arithmetic functions efficiently or effectively—
these functions require high logic cell usage while garnering only moderate performance results.
The QL58x2 device family architecture allows for functionality above and beyond that achievable using
programmable logic devices. By embedding a dynamically reconfigurable computational unit, the QL58x2
device family can address various arithmetic functions efficiently. This approach offers greater performance
and utilization than traditional programmable logic implementations. The embedded block is implemented at
the transistor level as shown in Figure 6.
Figure 6: ECU Block Diagram
The QL58x2 device family ECU blocks (Table 9) are placed next to the SRAM circuitry for efficient
memory/instruction fetch and addressing for DSP algorithmic implementations.
Up to twelve 8-bit MAC functions can be implemented per cycle for a total of 1 billion MACs/s when clocked
at 100 MHz. Additional multiply-accumulate functions can be implemented in the programmable logic.
The modes for the ECU block are dynamically re-programmable through the programmable logic.
Table 9: QL58x2 Device Family ECU Blocks
Device
ECUs
QL5842
12
QL5822
0
A[0:15]
B[0:15]
SIGN2
SIGN1
CIN
S1
S2
S3
A
B
C
D
3-4
decoder
8-bit
Multiplier
16-bit
Adder
17-bit
Register
2-1
mux
2-1
mux
3-1
mux
Q[16:0]
CLK
RESET
DQ
00
01
10
A[7:0]
A[15:8]
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