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參數(shù)資料
| 型號： | QL5232-33APB456I |
| 廠商： | QUICKLOGIC CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA456 |
| 封裝： | PLASTIC, BGA-456 |
| 文件頁數(shù)： | 2/21頁 |
| 文件大?。?/td> | 385K |
| 代理商： | QL5232-33APB456I |
62
Preliminary
QL5232 - QuickPCITM
3-62
QL5032 External Device Pins
Pin/Bus Name
Type
Function
AD[31:0]
T/S
PCI Address and Data: 32 bit multiplexed address/data bus.
CBEN[3:0]
T/S
PCI Bus Command and Byte Enables: Multiplexed bus which
contains byte enables for AD[31:0] or the Bus Command
during the address phase of a PCI transaction.
PAR
T/S
PCI Parity: Even Parity across AD[31:0] and C/BEN[3:0]
busses. Driven one clock after address or data phases. Mas-
ter drives PAR on address cycles and PCI writes. The Target
drives PAR on PCI reads.
FRAMEN
S/T/S
PCI Cycle Frame: Driven active by current PCI Master dur-
ing a PCI transaction. Driven low to indicate the address
cycle, driven high at the end of the transaction.
DEVSELN
S/T/S
PCI Device Select. Driven by a Target that has decoded a
valid base address.
CLK
IN
PCI System Clock Input.
RSTN
IN
PCI System Reset Input
REQN
T/S
PCI Request. Indicates to the Arbiter that this PCI Agent (Ini-
tiator) wishes to use the bus. A point to point signal between
the PCI Device and the System Arbiter.
GNTN
IN
PCI Grant. Indicates to a PCI Agent (Initiator) that it has
been granted access to the PCI bus by the Arbiter. A point to
point signal between the PCI device and the System
Arbiter.
PERRN
S/T/S
PCI Data Parity Error. Driven active by the initiator or target
two clock cycles after a data parity error is detected on the
AD and C/BE# busses.
SERRN
O/D
PCI System Error: Driven active when an address cycle par-
ity error, data parity error during a special cycle, or other
catastrophic error is detected.
IDSEL
IN
PCI Initialization Device Select. Use to select a specific PCI
Agent during System Initialization.
IRDYN
S/T/S
PCI Initiator Ready. Indicates the Initiator’s ability to com-
plete a read or write transaction. Data transfer occurs only
on clock cycles where both IRDYN and TRDYN are active.
TRDYN
S/T/S
PCI Target Ready. Indicates the Target’s ability to complete
a read or write transaction. Data transfer occurs only on
clock cycles where both IRDYN and TRDYN are active.
STOPN
S/T/S
PCI Stop. Used by a PCI Target to end a burst transaction.
INTAN
O/D
Interrupt A. Asynchronous Active-Low Interrupt Request.
QL5232 External Device Pins
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QL5432-33APQ208C-5846 | 制造商:QuickLogic Corporation 功能描述: |
| QL55M6XD30BQ | 制造商:Banner Engineering 功能描述:QL55M6XD30BQ LUMINESCENCE NPN/PNP M12 20 TO 40mm |
| QL55M6XD50BQ | 制造商:Banner Engineering 功能描述:QL55M6XD50BQ LUMINESCENCE NPN/PNP M12 40 TO 75mm |
| QL564 | 制造商:Aim & Thurlby Thandar Instruments 功能描述:PSU 56V 4A PECISION |
| QL564 SII | 制造商:Aim & Thurlby Thandar Instruments 功能描述:POWER SUPPLY, BENCH, ADJ, 1O/P, 56V, Power Supply Output Type:Adjustable, No. of Outputs:1, Output Voltage Min:0V, Output Voltage Max:56V, Output Current Min:0A, Output Current Max:4A, Power Rating:112W, Input Voltage:115VAC / 230VAC, RoHS Compliant: NA 制造商:TTI (THURLBY THANDAR INSTRUMENTS) 功能描述:POWER SUPPLY, BENCH, ADJ, 1O/P, 56V, Power Supply Output Type:Adjustable, No. of |
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