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參數(shù)資料
| 型號： | QL3004 |
| 廠商： | QuickLogic Corp. |
| 英文描述： | pASIC 3 FPGA Family High Performance and High Density with Low Cost and Complete Flexibiltiy(具有低成本和充分靈活性的高性能和高密度的pASIC 3現(xiàn)場可編程門陣列) |
| 中文描述： | 帕希奇3 FPGA系列高性能與高密度的低成本和完整Flexibiltiy（具有低成本和充分靈活性的高性能和高密度的帕希奇3現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 254K |
| 代理商： | QL3004 |
8
Preliminary
7-8
pASIC 3 FPGA
TM
Family
on design constraints and connectivity) to ensure the
optimum speed/density combination.
The pASIC 3 Family is based on a 0.35 micron high-
volume CMOS fabrication process with the ViaLink
programmable-via antifuse technology inserted
between the metal deposition steps. The ViaLink ele-
ment exists in one of two states: a highly resistive
unprogrammed OFF state and the low impedance,
programmed ON state. Programmed ViaLink ele-
ments connect the outputs of one logic cell to the
inputs of other logic cells directly or in combination
with other links. An unprogrammed link experiences
a worst case voltage equal to VCC biased across its
terminals. A programmed link carries A.C. current
caused by charging and discharging of device and
interconnect capacitances during switching. No D.C.
current flows through either a programmed or an
unprogrammed link during operation as a logic
device.
Studies of test structures and complete pASIC
devices have shown that an unprogrammed link
under VCC bias remains in the unprogrammed state
over time. Similar tests on programmed links under
current bias exhibit the same stability. These tests
indicate that the long term reliability of the combined
CMOS and ViaLink structure is similar to that of the
base CMOS process. For further details, contact
QuickLogic.
Propagation delays depend on routing, fanout, load
capacitance, supply voltage, junction temperature,
and process variation. The AC Characteristics in
each individual device data sheet are a design guide
to provide initial timing estimates at nominal condi-
tions. Worst case estimates are obtained when nomi-
nal propagation delays are multiplied by the
appropriate Delay Factor, K, as specified in the Delay
Factor table (Operating Range). The QuickWorks-
Lite/QuickTools/QuickWorks software incorporates
data sheet AC Characteristics into the design data-
base for pre-place-and-route timing analysis. The
SpDE Delay Modeler extracts specific timing parame-
ters for precise path analysis or simulation results fol-
lowing place and route.
The following diagrams provide timing models for
several of the most common paths in the devices.
These models can be used with the
"K Factor" and "AC Characteristics" information (in
the individual device data sheets) to estimate timing.
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