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參數(shù)資料
| 型號(hào)： | QL3004 |
| 廠商： | QuickLogic Corp. |
| 英文描述： | pASIC 3 FPGA Family High Performance and High Density with Low Cost and Complete Flexibiltiy(具有低成本和充分靈活性的高性能和高密度的pASIC 3現(xiàn)場可編程門陣列) |
| 中文描述： | 帕希奇3 FPGA系列高性能與高密度的低成本和完整Flexibiltiy（具有低成本和充分靈活性的高性能和高密度的帕希奇3現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 254K |
| 代理商： | QL3004 |
7-3
pASIC 3 FPGA
TM
Family
or simulation. QuickTools and QuickWorks-Lite read
EDIF netlists and provide optimization, place and
route, timing analysis, and back-annotation support
for all QuickLogic devices. QuickTools and Quick-
Works-Lite also write out OVI, VITAL, VSS, EDIF,
LMC, SDF, and Viewsim files to support a wide
range of third-party modeling and simulation tools.
Logic Cell and RAM Module Organization
L
OGIC
C
ELL
AND
RAM M
ODULE
O
RGANIZATION
The pASIC 3 family contains devices covering a wide
spectrum of density requirements. The Five mem-
bers range from 96 logic cells to 1,584 logic cells
arranged in regular two-dimensional arrays. Horizon-
tal and vertical routing channels containing up to
thirty wires run above the logic cells to connect func-
tions.
Each logic cell includes one pre-configured register,
plus the logic to implement an additional indepen-
dent latch. Therefore, users have up to three fully
independent flip-flops for every two logic cells. Since
each input and I/O cell also include a register, the
total number of available flip-flops in a device equals
the number of logic cells multiplied by 1.5 plus the
total number of I/O pins. For example, the QL3025
has: (672 logic cells x 1.5) + (204 I/O cells) = 1212
available flip-flops.
.ViaLink
Programming Element
Programmable devices implement customer-defined
logic functions by interconnecting user-configurable
logic cells through a variety of semiconductor switch-
ing elements. The maximum speed of operation is
determined by the effective impedance of the switch
in both programmed ON, and unprogrammed OFF
states.
In pASIC 3 devices the switch is called a ViaLink ele-
ment. The ViaLink element is an antifuse formed in a
via between the metal three and metal four layers of a
four-layer metal CMOS process. The direct metal-to-
metal link, created as a result of programming,
achieves a connection with resistance values below
50 ohms. This is less than 5 percent of the resistance
of an EPROM or SRAM switch and 10 percent of
that of a dielectric antifuse. The capacitance of an
unprogrammed ViaLink site is also lower than these
alternative approaches. The resulting low RC time
constant provides speeds up to two times faster than
older generation technologies.
Figure 2 shows a programmed ViaLink site. In a cus-
tom metal-masked ASIC, such as a gate array, the
top and bottom layers of metal make direct contact
through a tungsten-plug via. In a ViaLink-program-
mable ASIC device the two layers of metal are ini-
tially separated by an insulating amorphous silicon
layer with resistance in excess of 1 gigaohm.
A programming voltage applied across the via forms
a bidirectional conductive link connecting the second
and third metal layers, as shown in the microphoto-
graph of the ViaLink element in the figure above.
FIGURE 2. ViaLink
Element
V
IA
L
INK
P
ROGRAMMING
E
LEMENT
{
{
ViaLink
Amorphous
Silicon
Antifuse
Metal 4
Tungsten
Plug
Metal 3
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| QL3012 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:60,000 Usable PLD Gate pASIC3 FPGA Combining High Performance and High Density |
| QL3012-0PF100C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| QL3012-0PF100C-5224 | 制造商:QuickLogic Corporation 功能描述:QLGQL3012-0PF100C-5224 QL3012-0PF100C-52 |
| QL3012-0PF100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
| QL3012-0PF100I-5762 | 制造商:QuickLogic Corporation 功能描述: |
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