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參數(shù)資料
| 型號： | QL3004 |
| 廠商： | QuickLogic Corp. |
| 英文描述： | pASIC 3 FPGA Family High Performance and High Density with Low Cost and Complete Flexibiltiy(具有低成本和充分靈活性的高性能和高密度的pASIC 3現(xiàn)場可編程門陣列) |
| 中文描述： | 帕希奇3 FPGA系列高性能與高密度的低成本和完整Flexibiltiy（具有低成本和充分靈活性的高性能和高密度的帕希奇3現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 254K |
| 代理商： | QL3004 |
6
Preliminary
7-6
pASIC 3 FPGA
TM
Family
This level of flexibility is especially important for
designs synthesized from HDLs such as VHDL or
Verilog. Typically, synthesis tools prefer "gate array-
like" fine-grained architectures; however, fine-grained
FPGA architectures generally yield very poor perfor-
mance due to the long delays resulting from building
functions with multiple levels of gates and slow inter-
connect elements. The pASIC 3 family gives logic
synthesis tools the needed degrees of freedom for the
high logic utilization benefits of a fine-grained archi-
tecture without sacrificing the high performance ben-
efits of a large-grained, high fan-in architecture.
The pASIC 3 macro library contains more than 400
of the most frequently used logic functions optimized
to fit the logic cell architecture. A detailed under-
standing of the logic cell is therefore not necessary to
design successfully with pASIC 3 devices. CAE tools
will automatically map a conventional logic schematic
or HDL file into a device and provide excellent per-
formance and utilization.
I/O Features
The pASIC 3 family features three distinct types of
pins to maximize performance, functionality and flex-
ibility: bidirectional I/O pins, input-only pins, and
JTAG pins.
Bidirectional pins can be programmed for input, out-
put, or bidirectional operation. As shown in Figure 7,
each bidirectional I/O pin is associated with an I/O
cell which features a two-input OR gate, a three-state
output buffer, an input buffer, and an input/feedback
register. The OR gate allows active high or active low
outputs, or can be used for high-speed logical OR
functions independently of internal logic cells. The
three-state buffer fed by the OR gate allows the I/O
pin to act as an input or output. The buffer
’
s output
enable can be individually controlled through the
logic cell array or any pin, or bank-controlled through
one of two global networks.
FIGURE 7. I/O Cell
For output functions, I/O pins can be individually
configured for active HIGH, active LOW, or open-
drain inverting operation. In the active HIGH and
active LOW modes, the pins of higher speed grade
devices are fully PCI-drive compliant. In addition, all
I/Os are designed to ensure quiet switching charac-
teristics while maintaining high speed.
For input functions, I/O pins can provide combinato-
rial or registered data back to the logic array. For
registered input operation, I/O pins drive the D input
of I/O cell registers, allowing data to be captured
with fast set-up times without consuming internal
logic cell resources. When I/O pins are unused, the
OE controls can be permanently enabled, allowing
the I/O cell registers to be used for registered feed-
back into the logic array. I/O cell registers are con-
trolled by clock, clock enable, and reset signals,
which can come from the logic array, any pin, or
from one of the two global networks.
I/O F
EATURES
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