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參數(shù)資料
| 型號(hào)： | Q67121C452 |
| 英文描述： | IC-SM-8-BIT CPU-12MHZ |
| 中文描述： | 集成電路釤8位CPU - 12MHz的 |
| 文件頁數(shù)： | 23/121頁 |
| 文件大?。?/td> | 1000K |
| 代理商： | Q67121C452 |
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Memory Organization
C501
Semiconductor Group
3-2
3.1
Program Memory, “Code Space”
The C501-1R/-1E has 8 Kbytes of read-only/OTP program memory, while the C501-L has no
internal program memory. The program memory can be externally expanded up to 64 Kbytes. If the
EA pin is held high, the C501 executes out of internal program memory unless the address exceeds
1FFFH. Locations 2000H through FFFFH are then fetched from the external program memory. If
the EA pin is held low, the C501 fetches all instructions from the external program memory.
3.2
Data Memory, “Data Space”
The data memory address space consists of an internal and an external memory space. The
internal data memory is divided into three physically separate and distinct blocks : the lower
128 bytes of RAM, the upper 128 bytes of RAM, and the 128 byte special function register (SFR)
area.
While the upper 128 bytes of data memory and the SFR area share the same address locations,
they are accessed through different addressing modes. The lower 128 bytes of data memory can
be accessed through direct or register indirect addressing; the upper 128 bytes of RAM can be
accessed through register indirect addressing; the special function registers are accessible through
direct addressing. Four 8-register banks, each bank consisting of eight 8-bit multi-purpose registers,
occupy locations 0 through 1FH in the lower RAM area. The next 16 bytes, locations 20H through
2FH, contain 128 directly addressable bit locations. The stack can be located anywhere in the
internal data memory address space, and the stack depth can be expanded up to 256 bytes.
The external data memory can be expanded up to 64 Kbyte and can be accessed by instructions
that use a 16-bit or an 8-bit address.
3.3
General Purpose Registers
The lower 32 locations of the internal RAM are assigned to four banks with eight general purpose
registers (GPRs) each. Only one of these banks may be enabled at a time. Two bits in the program
status word, RS0 and RS1, select the active register bank (see description of the PSW in
chapter 2
). This allows fast context switching, which is useful when entering subroutines or
interrupt service routines.
The 8 general purpose registers of the selected register bank may be accessed by register
addressing. With register addressing the instruction op code indicates which register is to be used.
For indirect addressing R0 and R1 are used as pointer or index register to address internal or
external memory (e.g. MOV @R0).
Reset initializes the stack pointer to location 07H and increments it once to start from location 08H
which is also the first register (R0) of register bank 1. Thus, if one is going to use more than one
register bank, the SP should be initialized to a different location of the RAM which is not used for
data storage.
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