- 您現(xiàn)在的位置：買(mǎi)賣IC網(wǎng) > PDF目錄361233 > Q67100-A6059 (SIEMENS AG) Primary Rate Access Clock Generator and Transceiver PRACT PDF資料下載
參數(shù)資料
| 型號(hào)： | Q67100-A6059 |
| 廠商： | SIEMENS AG |
| 英文描述： | Primary Rate Access Clock Generator and Transceiver PRACT |
| 中文描述： | 主速率接入時(shí)鐘發(fā)生器和收發(fā)PRACT |
| 文件頁(yè)數(shù)： | 9/53頁(yè) |
| 文件大小： | 418K |
| 代理商： | Q67100-A6059 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)當(dāng)前第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)
HYB 39S64400/800/160BT(L)
64-MBit Synchronous DRAM
Data Book
9
12.99
Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the truth table for the operation commands.
Notes
1.
V = Valid, x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock
before the commands are provided.
3. This is the state of the banks designated by BA0, BA1 signals.
4. Device state is Full Page Burst operation
5. Power Down Mode can not entry in the burst cycle. When this command assert in the burst mode
cycle device is clock suspend mode.
Operation
Device
State
Idle
3
Active
3
Active
3
CKE
n-1
CKE
n
CS
RAS
CAS
WE
DQM A0-9,
A11
A10
BA0
BA1
Row Activate (ACT)
H
X
L
L
H
H
X
V
V
V
Read (READ)
H
X
L
H
L
H
X
V
L
V
Read w/ Autoprecharge
(READA)
H
X
L
H
L
H
X
V
H
V
Write (WRITE)
Active
3
Active
3
H
X
L
H
L
L
X
V
L
V
Write w/ Autoprecharge
(WRITEA)
H
X
L
H
L
L
X
V
H
V
Row Precharge (PRE)
Any
H
X
L
L
H
L
X
X
L
V
Precharge All (PREA)
Any
H
X
L
L
H
L
X
X
H
X
Mode Register Set (MRS)
Idle
H
X
L
L
L
L
X
V
V
V
No Operation (NOP)
Any
H
X
L
H
H
H
X
X
X
X
Device Deselect (INHBT)
Any
H
X
H
X
X
X
X
X
X
X
Auto Refresh (REFA)
Idle
H
H
L
L
L
H
X
X
X
X
Self Refresh Entry (REFS-EN) Idle
H
L
L
L
L
H
X
X
X
X
Self Refresh Exit (REFS-EX)
Idle
(Self
Refr.)
L
H
H
X
X
X
X
X
X
X
L
H
H
X
Power Down Entry (PDN-EN) Idle
Active
5
H
L
H
X
X
X
X
X
X
X
L
H
H
X
Power Down Exit (PDN-EX)
Any
(Power
Down)
L
H
H
X
X
X
X
X
X
X
L
H
H
L
Data Write/Output Enable
Active
H
X
X
X
X
X
L
X
X
X
Data Write/Output Disable
Active
H
X
X
X
X
X
H
X
X
X
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| Q67100-H3217 | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| Q67100-H3218 | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| Q67100-H3220 | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| Q67100-H3496 | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| Q67100-H3497 | 16 Kbit 2048 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus, Page Protection Mode |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Q67100-A8310 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Dimmer IC for Halogen Lamps |
| Q67100-A8315 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DIMMER IC FOR HALOGEN LAMPS |
| Q67100-H3022 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Peripheral Board Controller(PBC) |
| Q67100-H3217 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1/2 Kbit 128/256 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
| Q67100-H3218 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:1/2 Kbit 128/256 x 8 bit Serial CMOS EEPROMs, I2C Synchronous 2-Wire Bus |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。